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參數(shù)資料
| 型號(hào)： | HYS 72V16200GR |
| 廠商： | SIEMENS AG |
| 英文描述： | PC100 Registered SDRAM-Module(PC100 用于寄存的 SDRAM 模塊) |
| 中文描述： | 注冊(cè)PC100的內(nèi)存模塊（PC100的用于寄存的內(nèi)存模塊） |
| 文件頁數(shù)： | 21/22頁 |
| 文件大小： | 217K |
| 代理商： | HYS 72V16200GR |
HYS 72Vx2xxGR
PC100 Registered SDRAM-Modules
Data Book
21
3.00
Functional Description
All 168-pin Registered DIMMs conform to a compatible set of timing and operation characteristics
intended to comply with the 100 MHz standards. The Registered DIMMs achieve high speed data
transfer rate up to 100 MHz.
All control and address signals are synchronized with the positive edge of externally supplied clocks
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show
DIMM operation at the tabs, not SDRAM operation.
The picture below depicts an overview of the effect of the Registered Mode on the data outputs
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS
latency, in the case two clocks. With the register, the data is delayed according to the device CAS
latency plus an additional clock cycle. This is know as the DIMM CAS latency, and in this example
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens
the pipe by one clock cycle.
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on
each subsequent rising clock edge until the burst length is completed. When the burst has finished,
any additional data supplied to the DQ pins will be ignored.
SPT03968
CLK
Read A
T0
T1
T2
T3
T4
T5
T6
Command
DOUT A0
DOUT A1 DOUT A2 DOUT A3
NOP
NOP
NOP
NOP
NOP
CAS latency = 2
, DQ’s
CK2
t
Registered DIMM Burst Read Operation (BL = 4)
Device
NOP
DOUT A1
DOUT A0
DOUT A2 DOUT A3
CAS latency = 3
, DQ’s
CK3
DIMM
t
One Clock
Added for on-DIMM pipeline register
Reg-DIMM Latency = 1
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