參數(shù)資料
型號: HYS64D16000GDL-7-B
廠商: INFINEON TECHNOLOGIES AG
英文描述: Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:10ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
中文描述: 200引腳小外型雙列直插內(nèi)存模塊
文件頁數(shù): 15/31頁
文件大?。?/td> 777K
代理商: HYS64D16000GDL-7-B
Data Sheet
15
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2
Current Specification and Conditions
Table 8
Parameter
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE
V
IL,MAX
Precharge Floating Standby Current
CS
V
IH,MIN
, all banks idle; CKE
V
IH,MIN
;
address and other control inputs changing once per clock cycle;
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current
CS
V
IH,MIN
, all banks idle; CKE
V
IH,MIN
;
V
IN
=
V
REF
for DQ, DQS and DM;
address and other control inputs stable at
V
IH,MIN
or
V
IL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Standby Current
one bank active; CS
V
IH,MIN
; CKE
V
IH,MIN
;
t
RC
=
t
RAS,MAX
;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B;
I
OUT
= 0 mA
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current
CKE
0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
I
DD
Conditions
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
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