參數(shù)資料
型號： HYS64D16000GDL-7-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:10ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
中文描述： 200引腳小外型雙列直插內(nèi)存模塊
文件頁數(shù)： 22/31頁
文件大?。?/td> 777K
代理商： HYS64D16000GDL-7-B
Data Sheet
22
V1.2, 2003-08
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
V
OH(ac)
and
V
OL(ac)
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
t
RPRES
is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
相關(guān)PDF資料
PDF描述
HYS64D16000GDL-8-B Network Cable Assembly; Connector Type A:T568A/B Modular Plug; Connector Type B:T568A/B Modular Plug; Cable Length:15ft; Approval Categories:Augmented Category 6 standards; cord color per TIA/EIA-606 standard RoHS Compliant: Yes
HYS64D16000GU-7-A Unbuffered DDR SDRAM-Modules
HYS72D16000GU-7-A Unbuffered DDR SDRAM-Modules
HYS64D32020GU-7-A Unbuffered DDR SDRAM-Modules
HYS72D32020GU-7-A Unbuffered DDR SDRAM-Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS64D16000GDL-8-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D16000GU-7-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM-Modules
HYS64D16000GU-8-A 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM-Modules
HYS64D16000HDL-6-C 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D16001GDL-6-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules
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