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參數(shù)資料
| 型號： | HYS64D16020GD |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Unbuffered DDR SDRAM SO Modules |
| 中文描述： | 無緩沖DDR SDRAM的蘇模塊 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 963K |
| 代理商： | HYS64D16020GD |
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Electrical Characteristics
Data Sheet
18
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between
V
OH(ac)
and
V
OL(ac)
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
t
RPRES
is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
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