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參數(shù)資料
| 型號： | HYS64D16020GD |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Unbuffered DDR SDRAM SO Modules |
| 中文描述： | 無緩沖DDR SDRAM的蘇模塊 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 963K |
| 代理商： | HYS64D16020GD |
HYS64D16020GD(L)-[7/8]-A
Unbuffered DDR SDRAM SO Modules
Pin Configuration
Data Sheet
8
Rev. 1.02, 2004-01
11042003-YIV7-VK6M
2
Pin Configuration
Note:S1 and CKE1 are used on two rank modules only
Table 3
Symbol
A0 - A11
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS, CAS, WE
CKE0 - CKE1
DQS0 - DQS8
CK0 - CK2,
CK0 - CK2
DM0 - DM8
DQS9 - DQS17
S0, S1
V
DD
V
SS
V
DDQ
V
DDID
V
REF
V
DDSPD
SCL
SDA
SA0 - SA2
NC
Pin Definitions and Functions
Type
1)
I
I
I/O
I/O
I
I
I/O
I
I
I
I/O
I
PWR
GND
PWR
PWR
AI
PWR
I
I/O
I
NC
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Function
Address Inputs
Bank Selects
Data Input/Output
Check Bits (
×
72 organization only)
Command Inputs
Clock Enable
SDRAM low data strobes
SDRAM clock (positive lines)
SDRAM clock (negative lines)
SDRAM low data mask/
high data strobes
Chip Selects for Rank0 and Rank1
Power (+2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
Serial bus data line
slave address select
Not Connected
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