參數(shù)資料
型號(hào)： HYS64D32020GDL-6-C
廠(chǎng)商： INFINEON TECHNOLOGIES AG
英文描述： 200-Pin Small Outline Dual-In-Line Memory Modules
中文描述： 200引腳小外型雙列直插內(nèi)存模塊
文件頁(yè)數(shù)： 20/30頁(yè)
文件大?。?/td> 874K
代理商： HYS64D32020GDL-6-C
15
—
Data Sheet
20
Rev. 1.0, 2004-03
HYS64D[32020/16000][H/G]DL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Address and control input hold
time
t
IH
0.6
—
0.75
—
ns
fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
t
RPRE
t
RPST
t
RAS
t
RC
0.9
0.40
40
55
1.1
0.60
70E+3
—
0.9
0.40
42
60
1.1
0.60
70E+3
—
t
CK
t
CK
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
t
RFC
65
—
72
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
15
15
t
RCD
or t
RASmin
—
—
18
18
t
RCD
or t
RASmin
—
—
ns
ns
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t
RRD
10
—
12
—
ns
2)3)4)5)
t
WR
t
DAL
15
—
ns
t
CK
2)3)4)5)
—
—
—
—
2)3)4)5)11)
t
WTR
2
—
1
—
t
CK
2)3)4)5)
t
XSNR
75
—
75
—
ns
2)3)4)5)
t
XSRD
200
—
200
—
t
CK
2)3)4)5)
t
REFI
—
7.8
—
7.8
μ
s
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Table 12
Parameter
AC Timing - Absolute Specifications for DDR400B and DDR333
(cont’d)
Symbol
DDR400B
Min.
–5
–6
Unit
Note/ Test
Condition
1)
DDR333
Min.
Max.
Max.
相關(guān)PDF資料
PDF描述
HYS64D32020GDL-5-C 200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D32020GDL5C 200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D32020HDL-5-C 200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D64020GBDL-6-C 200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D64020GBDL-5-C 200-Pin Small Outline Dual-In-Line Memory Modules
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS64D32020GDL-7B 制造商:Infineon Technologies AG 功能描述:
HYS64D32020GDL-7-B 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D32020GDL-8-B 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:200-Pin Small Outline Dual-In-Line Memory Modules
HYS64D32020GU-7-A 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM-Modules
HYS64D32020GU-8-A 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Unbuffered DDR SDRAM-Modules
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