參數(shù)資料
型號: HYS64T128020GU-5-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: CAPACITOR-CERAMIC
中文描述: 240針無緩沖DDR2 SDRAM內(nèi)存模塊
文件頁數(shù): 25/67頁
文件大小: 1527K
代理商: HYS64T128020GU-5-A
HYS[64T[3200/6400/12802]0/72T[6400/12802]0][G/H]U–[3.7/5]–A
512 Mbit DDR2 SDRAM
I
DD
Specifications and Conditions
Data Sheet
25
Rev. 0.87, 2004-06
09122003-GZEK-H4J6
Self-Refresh Current
CKE
0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING,
Data bus inputs are FLOATING. RESET = Low.
I
DD6
current values are guaranteed up to
T
CASE
of 85
°
C
max.
All Bank Interleave Read Current
All banks are being interleaved at minimum
t
RC
without violating
t
RRD
using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS.
I
out
= 0 mA.
1)
V
DDQ
= 1.8 V
±
0.1 V;
V
DD
= 1.8 V
±
0.1 V
2) For details and notes see the relevant INFINEON component data sheet
I
DD6
I
DD7
Table 17
Product Type
I
DD
Specification
H
256MB
×
64
1 Rank
–3.7
Max.
320
360
16
160
120
64
20
160
400
440
520
24
16
880
H
H
512MB
×
64
1 Rank
–3.7
Max.
520
600
32
320
240
128
40
320
720
760
1040
48
32
1120
H
H
512MB
×
72
1 Rank
–3.7
Max.
585
675
36
360
270
144
45
360
810
855
1170
54
36
1260
H
H
1GB
×
64
2 Ranks
–3.7
Max.
552
632
64
640
480
256
80
640
752
792
1072
96
64
1152
H
H
1GB
×
72
2 Ranks
–3.7
Max.
621
711
72
720
540
288
90
720
846
891
1206
108
72
1296
H
Unit
Notes
Organization
Symbol
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P( MRS = 0)
I
DD3P( MRS = 1)
I
DD3N
I
DD4R
I
DD4W
I
DD5B
I
DD5D
I
DD6
I
DD7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)
1) Calculated values from component data. ODT disabled.
I
DD1
,
I
DD4R
and
I
DD7
are defined with the outputs disabled
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
Table 16
Parameter
I
DD
Measurement Conditions
1)2)
(cont’d)
Symbol
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