參數(shù)資料
型號: HYS72D32020GU-8-A
廠商: INFINEON TECHNOLOGIES AG
英文描述: Unbuffered DDR SDRAM-Modules
中文描述: 無緩沖DDR SDRAM內(nèi)存模塊
文件頁數(shù): 26/30頁
文件大?。?/td> 881K
代理商: HYS72D32020GU-8-A
65 ns
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
Data Sheet
26
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z
27
Minimum Row Precharge
Time
Minimum Row Act. to Row
Act. Delay
t
RRD
Minimum RAS to CAS Delay
t
RCD
Minimum RAS Pulse Width
t
RAS
Module Bank Density (per
Bank)
Addr. and Command Setup
Time
Addr. and Command Hold
Time
Data Input Setup Time
Data Input Hold Time
Superset Information
Minimum Core Cycle Time
t
RC
Min. Auto Refresh Cmd
Cycle Time
t
FRC
Maximum Clock Cycle Time
t
CK
Max. DQS-DQ Skew tDQSQ 0.5 ns
X-Factor tQHS
Superset Information
SPD Revision
Checksum for Bytes 0 - 62
Manufactures
JEDEC
Codes
Manufactures
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
128 to 255 open for Customer use
20 ns
50
50
50
50
28
15 ns
3C
3C
3C
3C
29
20 ns
50
50
50
50
30
45 ns
2D
2D
2D
2D
31
128 MByte
20
20
20
20
32
0.9 ns
90
90
90
90
33
0.9 ns
90
90
90
90
34
35
36 to 40
41
0.5 ns
0.5 ns
50
50
50
50
50
50
50
50
41
41
41
41
42
75 ns
4B
4B
4B
4B
43
12 ns
30
30
30
30
44
45
46 to 61
62
63
64
32
75
00
00
8F
C1
32
75
00
00
8F
C1
32
75
00
00
8F
C1
32
75
00
00
8F
C1
0.75 ns
Revision 0.0
ID
65 to 71
72
73 to 90
91 to 92
93 to 94
95 to 98
99 to 127
Infineon
Infineon
Infineon
Infineon
Table 12
Byte#
SPD Codes for PC2100 Modules -7
(cont’d)
Description
128MB
x64
1rank
–7
hex.
128MB
x72
1rank
–7
hex.
128MB
x64
2ranks
–7
hex.
128MB
x64
2ranks
–7
hex.
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PDF描述
HYS64D16020GDL-8-A Unbuffered DDR SDRAM SO Modules
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HYS64D16020GDL-7-A Unbuffered DDR SDRAM SO Modules
HYS64D32020GDL-6-C 200-Pin Small Outline Dual-In-Line Memory Modules
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