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參數(shù)資料
| 型號： | HYS72T64020GR-5-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | DDR2 Registered DIMM Modules |
| 中文描述： | 注冊的DDR2內(nèi)存模組 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大小： | 725K |
| 代理商： | HYS72T64020GR-5-A |
HYS72Txx0xxGR
Registered DDR2 SDRAM-Modules
INFINEON Technologies
16
2.04
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade
(Component level data, for reference only)
Symbol
Parameter
-5
DDR2 -400
-3.7
DDR2 -533
-3
DDR2 -667
Unit
Min
Max
Min
Max
Min
Max
t
AC
DQ output access time from CK / CK
600
+
600
-500
+500
-450
+450
ps
t
DQSCK
DQS output access time from CK / CK
t
CH
CK, CK high-level width
t
CL
CK, CK low-level width
t
HP
Clock Half Period
500
+
500
450
+
450
-400
+400
ps
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
0.45
0.55
0.45
0.55
0.45
0.55
t
CK
min. (t
CL,
t
CH)
min. (t
CL,
t
CH)
min. (t
CL,
t
CH)
t
CK
Clock cycle time
CL = 3
5000
8000
5000
8000
5000
8000
ps
CL = 4 & 5
5000
8000
3750
8000
3000
8000
ps
t
IS
t
IH
t
DS
t
DH
t
IPW
t
DIPW
t
HZ
t
LZ(DQ)
DQ low-impedance from CK / CK
t
LZ(DQS)
DQS low-impedance from CK / CK
DQS-DQ skew
(for DQS & associated DQ signals)
Address and control input setup time
600
-
600
-
tbd.
-
ps
Address and control input hold time
600
-
600
-
tbd.
-
ps
DQ and DM input setup time
400
-
350
-
300
-
ps
DQ and DM input hold time
400
-
350
-
300
-
ps
Control and Addr. input pulse width (each input)
0.6
-
0.6
-
0.6
-
t
CK
DQ and DM input pulse width (each input)
0.35
-
0.35
-
0.35
-
t
CK
Data-out high-impedance time from CK / CK
-
tACmax
-
tACmax
-
tACmax
ps
2*tACmin
tACmax
2*tACmin
tACmax
2*tACmin
tACmax
ps
tACmin
tACmax
tACmin
tACmax
tACmin
tACmax
ps
t
DQSQ
-
350
-
300
-
250
ps
t
QHS
t
QH
Data hold skew factor
-
450
-
400
-
350
ps
Data Output hold time from DQS
t
HP
-t
QHS
WL
-0.25
-
t
HP
-t
QHS
WL
-0.25
-
t
HP
-t
QHS
WL
-0.25
-
t
DQSS
Write command to 1st DQS latching transition
WL
+0.25
WL
+0.25
WL
+0.25
t
CK
t
DQSL,H
DQS input low (high) pulse width (write cycle)
DQS falling edge to CLK setup time
(write cycle)
0.35
-
0.35
-
0.35
-
t
CK
t
DSS
0.2
-
0.2
-
0.2
-
t
CK
t
DSH
DQS falling edge hold time from CLK
(write cycle)
0.2
-
0.2
-
0.2
-
t
CK
t
MRD
t
WPRE
Write preamble
t
WPST
Write postamble
t
RPRE
Read preamble
t
RPST
Read postamble
t
RAS
Active to Precharge command
t
RC
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command
period
Mode register set command cycle time
2
-
2
-
2
-
t
CK
0.25
-
0.25
-
0.35
-
t
CK
0.40
0.60
0.40
0.60
0.40
0.60
t
CK
0.9
1.1
0.9
1.1
0.9
1.1
t
CK
0.40
0.60
0.40
0.60
0.40
0.60
t
CK
45
70000
45
70000
45
70000
ns
60
-
60
-
57
-
ns
t
RFC
75
-
75
-
75
-
ns
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| HYS72T32000GR-5-A | DDR2 Registered DIMM Modules |
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| HYS72T32000GR | DDR2 Registered DIMM Modules |
| HYS72T64020GR | DDR2 Registered DIMM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64020HR | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64020HR-2.5-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64020HR-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64020HR-3-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64020HR-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
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