參數(shù)資料
型號(hào): HYS72V16220GU-10
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module
中文描述: 16M X 72 SYNCHRONOUS DRAM MODULE, 8 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 10/17頁
文件大?。?/td> 84K
代理商: HYS72V16220GU-10
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Semiconductor Group
10
1998-08-01
Refresh Cycle
Refresh Period
(4096 cycles)
t
REF
64
64
64
ms
8
Self Refresh Exit Time
t
SREX
10
10
10
ns
9
Read Cycle
Data Out Hold Time
Data Out to Low Impedance
t
LZ
Data Out to High Impedance
t
HZ
DQM Data Out Disable
Latency
t
OH
3
3
3
ns
4
0
0
0
ns
3
8
3
10
3
10
ns
10
t
DQZ
2
2
2
CLK
Write Cycle
Data input to Precharge
(write recovery)
t
DPL
2
2
2
CLK
Data In to Active/Refresh
t
DAL
t
DQW
5
5
5
CLK
DQM Write Mask Latency
0
0
0
CLK
AC Characteristics
(cont’d)
3, 4
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 3.3 V
±
0.3 V,
t
T
= 1 ns
Parameter
Symbol
Limit Values
Unit
Note
-8
PC100-222
-8B
PC100-323
-10
PC66
min.
max.
min.
max.
min.
max.
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參數(shù)描述
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