參數(shù)資料
型號(hào): HYS72V64220GU-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
中文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 10/15頁
文件大?。?/td> 274K
代理商: HYS72V64220GU-8
HYS 64/72V64220GU
SDRAM-Modules
INFINEON Technologies
10
9.01
SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU
Byte
#
Description
SPD Entry Value
Hex
64M x 64
-7.5
80
08
04
0D
0A
02
40
00
01
75
54
00
82
-7
-8
0
1
2
3
4
5
6
7
8
9
10
11
12
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
Module Data Width (cont
d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
Access Time from Clock at CL = 3
DIMM Config
Refresh Rate/Type
128
256
SDRAM
13
10
2
64
0
LVTTL
7.5 / 10 ns
5.4 / 6 ns
non-ECC
Self-Refresh,
7.8
μ
s
x8
na
t
CCD
= 1 CLK
75
54
A0
60
13
14
15
SDRAM Width, Primary
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-
Back Random Column Address
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time at CL = 2
Access Time from Clock for CL = 2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from
Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active
Delay
t
RRD
Minimum RAS to CAS Delay
t
RCD
Minimum RAS Pulse Width
t
RAS
Module Bank Density (per bank)
SDRAM Input Setup Time
SDRAM Input Hold Time
08
00
01
16
17
18
19
20
21
22
23
24
25
26
1, 2, 4 & 8
4
CL = 2 & 3
CS latency = 0
Write latency = 0
unbuffered
V
DD
tol +/
10%
7.5 / 10.0 ns
5.4 / 6.0 ns
not supported
not supported
0F
04
06
01
01
00
0E
A0
60
FF
FF
75
54
00
00
A0
60
FF
FF
27
28
15 / 20 ns
14 / 15 / 16 ns
0F
0E
14
0F
14
10
29
30
31
32
33
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
0.8 / 1.0 ns
0F
2A
14
2D
40
15
08
14
32
15
08
20
10
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