參數(shù)資料
型號: HYS72V64220GU-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
中文描述: 64M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 6/15頁
文件大?。?/td> 274K
代理商: HYS72V64220GU-8
HYS 64/72V64220GU
SDRAM-Modules
INFINEON Technologies
6
9.01
Operating Currents per SDRAM Component
T
A
= 0 to 70
o
C,
V
DD
= 3.3 V
±
0.3 V
Parameter
Test
Condition
Symbol -7/ -7.5
-8
Unit Note
max.
Operating current
t
=
t
,
t
=
t
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
I
CC1
230
170
mA
1, 2
Precharge stand-by current
in Power Down Mode
CS =
V
IH(MIN.)
, CKE
V
IL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
t
CK
= min.
I
CC2P
2
2
mA
1, 2
CS =
V
IH (MIN.)
, CKE
V
IH(MIN.)
No operating current
t
CK
= min.
I
CC2N
40
30
mA
1, 2
t
CK
= min., CS =
V
IH(MIN.)
,
active state (max. 4 banks)
CKE
V
IH(MIN.)
I
CC3N
CKE
V
IL(MAX.)
I
CC3P
50
45
mA
1, 2
10
10
mA
1, 2
Burst operating current
t
= min.,
Read command cycling
I
CC4
150
100
mA
1,2,3
Auto refresh current
t
= min.,
Auto Refresh command cycling
I
CC5
240
220
mA
1, 2
Self refresh current
Self Refresh Mode, CKE = 0.2 V
I
CC6
3
3
mA
1
Notes
1. All values are shown per one SDRAM component.
2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation
frequency for -7 & -7.5 and at 100 MHz for -8 modules.
Input signals are changed once during
t
CK
, excepts for
I
CC6
and for stand-by currents when
t
= infinity.
3. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the
data out
current is excluded.
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