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參數(shù)資料
| 型號： | IA59032-CPGA100M |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 75K |
| 代理商： | IA59032-CPGA100M |
Page 14 of 17
Data Sheet
IA59032
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________
The End of Obsolescence
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT:
*Notes :
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase “Do Not Change” indicates that certain signals must remain LOW for the duration of the
clock LOW time. Otherwise, erroneous operation may be the result.
3) Prior to clock HIGH to LOW transition, source addresses must be stable to allow time for the
source data to be set up before the latch closes. After this transition the 'A' address may be changed. If it
is not being used as a destination, the B address may also be changed. If it is being used as a destination,
the B address must remain stable during the clock LOW period.
4)
Set-up time before HIGH to LOW included here.
Set up before
H to L
Hold after
H to L
Set up before
L to H
Hold after
L to H
UNITS
A,B Source Address
B Destination Address
D(31:0)
Cn
I(2:0)
I(5:3)
I(8:6)
RAM0,31 and Q0, 31
20
10
--
--
--
--
7
--
1 (note 3)
Do not change (note 2)
53 (note 4)
0
0
--
0
0
0
0
3
--
--
--
--
Do not change (note 2)
20
22
28
30
--
7
CP
ns
Input
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