![](http://datasheet.mmic.net.cn/Innovasic-Semiconductor/IA6805E2PLC44IR0_datasheet_97454/IA6805E2PLC44IR0_23.png)
IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Hi
Low
5
3
533
659
23
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
6
23
45
43
3
BTB 2
BSC 2
REL
1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
55
3
23
45
43
3BTB 2
BSC 2
REL
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
10
23
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
23
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
55
3
23
45
43
3BTB 2
BSC 2
REL
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
23
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
2
4
56
54
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
223
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
223
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
223
45
43
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
55
3
223
45
43
3
BTB 2
BSC 2
REL
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
65
2
34
32
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
433
64
265
67
65
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
1
INH 2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
2
23
45
43
3
BTB 2
BSC 2
REL
1
INH
2
IMM 2
DIR 3
EXT 3
IX2 2
IX1 1
IX
5
3
533
652
2
4
56
54
3
BTB 2
BSC 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
INH 1
INH
2
DIR 3
EXT 3
IX2 2
IX1 1
IX
IX1
IX2
IX
Branch
Read-Modify-Write
Control
Register/Memory
INH
IMM
DIR
EXT
F 1111
BTB
BSC
REL
DIR
INH
IX1
IX
INH
ROR
LSR
8
1000
7
0111
CMP
AND
LDA
CMP
SBC
CPX
AND
CMP
SBC
E
1110
F
1111
C
1100
D
1101
1010
AB
1011
9
1001
Bit Manipulation
RTS
5
0101
6
0110
0
0000
BRSET0
NEGA
2
0010
3
0011
4
0100
0
0000
BSET0
BRA
NEG
NEGX
NEG
RTI
SUB
BRCLR0
BCLR0
BRN
0 0000
1 0001
2 0010
BRSET1
BSET1
BHI
SBC
SWI
3 0011
CPX
4 0100
5 0101
COMA
COMX
COM
CPX
BIT
EOR
BRCLR1
BCLR1
BLS
COM
BIT
LDA
LSRA
AND
LSR
BRSET2
BSET2
BCC
LSR
LSRX
BIT
BRCLR2
BCLR2
BCS
A 1010
9 1001
7 0111
6 0110
8 1000
BIT
EOR
RORA
RORX
ROR
LDA
BRSET3
BSET3
BNE
ROR
D 1101
LDA
STA
EOR
C 1100
B 1011
E 1110
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
BRSET4
BSET4
BHCC
LSL
LSLA
LSLX
LSL
CLC
EOR
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
SEC
ADC
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
CLI
ORA
BRCLR5
BCLR5
BMI
SEI
ADD
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
RSP
JMP
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
NOP
BSR
JSR
BRSET7
BSET7
BIL
STOP
LDX
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
WAIT
TXA
STX
6
0110
7
0111
8
1000
1
0001
2
0010
3
0011
4
0100
D
1101
E
1110
F
1111
1
0001
9
1001
A
1010
B
1011
C
1100
5
0101
Abbreviations for Address
Modes:
Copyright 2007
IA211081401-03
www.Innovasic.com
Customer Support:
INH
Inherent
A
Accumulator
X
Index Register
IMM
Immediate
DIR
Direct
EXT
Extended
REL
Relative
BSC
Bit set/clear
SUB
3
IX
1
F
1111
0
0000
Opcode in Hexadecimal
Opcode in Binary
Address Mode
Mnemonic
Bytes
# of Cycles
BTB
Bit test and branch
IX
Indexed, no offset
IX1
Indexed, 1 byte offset
IX2
Indexed, 2 byte offset
Legend:
Page 23 of 33
1-888-824-4184