
IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Bus Timing
VSS=0V, TA=TL to TH (Figure 19)
Num
V
= 5.0V ±10%
DD
f
= 5MHz
OSC
1 TTL, 100pF Load
Unit
Parameters
Min
Max
1
Cycle Time
1000
DC
ns
2
Pulse Width, DS Low
587
-
ns
3
Pulse Width, DS High
403
-
ns
4
Clock Transition
-
4
ns
8
RW_n
9
-
ns
9
Non-Muxed Address Hold
97
-
ns
11
RW_n Delay From DS Fall
-
40
ns
16
Non-Muxed Address Delay From AS Rise
-
11
ns
17
MPU Read Data Setup
18
-
ns
18
Read Data Hold
0
ns
19
MPU Data Delay, Write
-
0
ns
21
Write Data Hold
204
-
ns
23
Muxed Address Delay From AS Rise
-
26
ns
24
Muxed Address Valid to AS Fall
185
-
ns
25
Muxed Address Hold
103
-
ns
26
Delay DS Fall to AS Rise
190
-
ns
27
Pulse Width, AS High
203
-
ns
28
Delay, AS Fall to DS Rise
185
-
ns
VLOW = 0.8V, VHIGH = VDD – 2.0V, VDD = 5.0V ±10%
TA = TL to TH, CL on Port = 50pF, fOSC = 5MHz
ADDRESS_STROBE
PORT_INPUT
PORT_OUTPUT
t
PVASL
t
ASLPX
t
ASLPV
*NOTE
*Note: The address strobe of the first cycle of the next instruction.
Figure 14. I/O Port Timing
Copyright 2007
IA211081401-03
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