參數(shù)資料
型號(hào)： IBM25EMPPC603EBG-100
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
封裝： 21 X 21 MM, 1.27 MM PITCH, 3 MM HEIGHT, CERAMIC, BGA-255
文件頁(yè)數(shù)： 42/42頁(yè)
文件大小： 509K
代理商： IBM25EMPPC603EBG-100
603e and EM603e Hardware Specification
9
Figure 1 provides the SYSCLK input timing diagram.
Figure 1. SYSCLK Input Timing Diagram
4
SYSCLK duty
cycle
measured at
1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
150
—
150
—
150
—
150
ps
4
603e and
EM603e
internal PLL-
relock time
—
100
—
100
—
100
—
100
s
3,5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description
in Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term
combined) must be under
±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during
the power-on reset sequence. This specication also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time (100
s) during the power-on reset sequence.
Table 7. Clock AC Timing Specifications (Continued)
Vdd = AVdd = 2.5
± 5% Vdc (= 3.3 ± 5% Vdc for PID6). O Vdd = 3.3 ± 5% Vdc. GND = 0 Vdc, 0 ≤ Tj ≤ 105°C.
Num
Characteristic
PID6
PID7v
PID7t
Unit
Notes
80 MHz
100 MHz
166 MHz
200 MHz
Min
Max
Min
Max
Min
Max
Min
Max
VM
CVil
CVih
SYSCLK
2
3
4
VM = Midpoint Voltage (1.4 V)
4
1
VM
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