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| 型號： | IBM25EMPPC603EFG-100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP240 |
| 封裝： | 32 X 32 MM, 4.10 MM HEIGHT, 0.50 MM PITCH, FP-240 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM25EMPPC603EFG-100 |
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2
603e and EM603e Hardware Specification
This document contains the following topics:
Topic
Page
To locate any published errata or updates for this document, contact the nearest IBM Microelectronics Sales
Representative, who can be located through the website at http://www.chips.ibm.com/products/embedded.
1.1 Overview
This section describes the features of the 603e and EM603e and describes briey how those units interact.
The 603e and EM603e are low-power implementations of the PowerPC microprocessor family of reduced
instruction set computing (RISC) microprocessors. The 603e and EM603e implement the 32-bit portion of
the PowerPC architecture specication, which provides 32-bit effective addresses, integer data types of 8,
16, and 32 bits, and oating-point data types of 32 and 64 bits.
The 603e and EM603e provide four software controllable power-saving modes. Three of the modes (the
nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated
by the processor. The fourth is a dynamic power management mode that causes the functional units in the
603e and EM603e to automatically enter a low-power mode when the functional units are idle without
affecting operational performance, software execution, or any external hardware.
The 603e and EM603e are superscalar processors capable of issuing and retiring as many as three
instructions per clock. Instructions can execute out of order for increased performance; however, the 603e
and EM603e make completion appear sequential.
The 603e and EM603e integrate ve execution units—an integer unit (IU), a oating-point unit (FPU) (the
FPU is not available on the EM603e), a branch processing unit (BPU), a load/store unit (LSU), and a system
register unit (SRU). The ability to execute ve instructions in parallel and the use of simple instructions with
rapid execution times yield high efciency and throughput for 603e- and EM603e-based systems. Most
integer instructions execute in one clock cycle. The FPU is pipelined, so a single-precision multiply-add
instruction can be issued every clock cycle.
The 603e and EM603e provide independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory management units
(MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside
buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and
variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement
algorithm. The 603e and EM603e also support block address translation through the use of two independent
instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective
addresses are compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the
BAT translation takes priority.
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