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參數(shù)資料
| 型號： | IBM25EMPPC750EBUB2330 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 233 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 2/43頁 |
| 文件大小： | 431K |
| 代理商： | IBM25EMPPC750EBUB2330 |
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Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
10 of 43
Figure 2. SYSCLK Input Timing Diagram
3.1.2.2 60x Bus Input AC Specications
Table 8 provides the 60X bus input AC timing specications for the PPC740 and
PPC750 as dened in Figure 3 and Figure 4 . Input timing specications for the L2 bus are
provided in Section 3.1.2.5, “L2 Bus Input AC Specications“.
Notes:
1. Input specications are measured from the TTL level (0.8 to 2.0 V) of the signal in question to the 1.4V
of the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see
2. Address/Data Transfer Attribute inputs are composed of the following--A[0-31], AP[0-3], TT[0-4],TBST,
TSIZ[0-2], GBL, DH[0-31), DL[0-31], DP[0-7].
3. All other signal inputs are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG,
DBWO, TA, DRTRY, TEA, DBDIS, TBEN, QACK, TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4 ).
5. tsysclk, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the
table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the
parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specication is for conguration mode select only. Also note that the HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset
sequence.
Table 8. 60X Bus Input Timing Specications1
Operating conditions are specied in Section Table 2., "Recommended Operating Conditions"
Num
Characteristic
Min
Max
Unit
Notes
10a
Address/Data/Transfer Attribute Inputs Valid to SYSCLK
(Input Setup)
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input Setup)
3.0
—
ns
3
10c
Mode Select Input Setup to HRESET (DRTRY,TLBISYNC)
8—
tsysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute Inputs
Invalid (Input Hold)
1.0
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input Hold)
1.0
—
ns
3
11c
HRESET
to mode select input hold (DRTRY, TLBISYNC)
0
—
ns
4,6,7
VM
CVil
CVih
VM = Midpoint Voltage (1.4 V)
1
2
4
SYSCLK
3
4
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