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| 型號： | IBM25PPC405GP3EE200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA413 |
| 封裝： | 25 MM, PLASTIC, EBGA-413 |
| 文件頁數(shù)： | 52/60頁 |
| 文件大?。?/td> | 1480K |
| 代理商： | IBM25PPC405GP3EE200CZ |
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PowerPC 405GP Embedded Processor Data Sheet
Page 56 of 60
6/20/03
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is
read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest
SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or
pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k
to
+3.3V or 10 k
to +5V. The recommended pull-down is 1K to GND. These pins are use for strap functions
only during reset. They are used for other signals during normal operation. The following table lists the
strapping pins along with their functions and strapping options. The pin for the 456-ball package is listed first
(for example, AF3), followed by the corresponding pin for the 413-ball package (for example, U8), which
appears as AF3/U8. The signal names assigned to the pins for normal operation follow the pin numbers.
PPC405GP Strapping Pin Assignments (Part 1 of 2)
Function
Option
Ball Strapping
PLL Tuning 1
for 6
≤ M ≤ 7 use choice 3
for 7 < M
≤ 12 use choice 5
for 12 < M
≤ 32 use choice 6
AF3/U8
UART0_Tx
AF2/T8
UART0_DTR
AD16/AB15
UART0_RTS
Choice 1; TUNE[5:0] = 010001
0
Choice 2; TUNE[5:0] = 111011
0
1
Choice 3; TUNE[5:0] = 010011
0
1
0
Choice 4; TUNE[5:0] = 111101
0
1
Choice 5; TUNE[5:0] = 010101
1
0
Choice 6; TUNE[5:0] = 010110
1
0
1
Choice 7; TUNE[5:0] = 111110
1
0
Choice 8; TUNE[5:0] = 100100
1
PLL Forward Divider 2
D16/A17
DMAAck0
B15/B14
DMAAck1
Bypass mode
0
Divide by 3
0
1
Divide by 4
1
0
Divide by 6
1
PLL Feedback Divider 2
B14/A15
DMAAck2
C12/A8
DMAAck3
Divide by 1
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
PLB Divider from CPU 2
P25/R23
EMCTxD3
L24/J22
EMCTxD2
Divide by 1
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
OPB Divider from PLB 2
L25/K21
EMCTxD1
J26/F22
EMCTxD0
Divide by 1
0
Divide by 2
0
1
Divide by 3
1
0
Divide by 4
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25PPC405GP-3BE200C | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA456 |
| IBM25PPC405GP-3EE266C | 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA413 |
| IBM25PPC405GP-3DE266CZ | 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA456 |
| IBM25PPC405GP-3BE133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA456 |
| IBM25PPC405GPR-3BA333CZ | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA456 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC405GP-3EE266C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|413PIN|PLASTIC |
| IBM25PPC405GP3EE266CZ | 制造商:IBM 功能描述: |
| IBM25PPC405GPR3BB266 | 制造商:IBM 功能描述: |
| IBM25PPC405-GPR-3JB266Z | 制造商:IBM 功能描述: |
| IBM25PPC405GPR-3KB266C | 制造商:IBM 功能描述: |
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