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參數(shù)資料
| 型號： | IBMB3N16644HCB-75AT |
| 英文描述： | x64 SDRAM Module |
| 中文描述： | X64的內(nèi)存模塊 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | IBMB3N16644HCB-75AT |
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 20
IBM13N16644HCC
IBM13N16734HCC
16M x 64/72 Two-Bank Unbuffered SDRAM Module
19L7296.E93875B
12/99
Mode Register Set Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
RSC
Mode Register Set Cycle Time
2
—
2
—
2
—
clk
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
OH
Data Out Hold Time
2.5
—
2.5
—
2.5
—
ns
2
3
—
3
3
ns
3
t
LZ
Data Out to Low Impedance Time
0
—
0
—
0
—
ns
t
HZ3
Data Out to High Impedance Time
3
6
3
6
3
7
ns
1
t
HZ2
Data Out to High Impedance Time
3
6
3
8
3
8
ns
1
t
DQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
CLK
1
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
2. AC Output Load Circuit A.
3. AC Output Load Circuit B.
Refresh Cycle
Symbol
Parameter
-260
-360
-10
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
REF
Refresh Period
—
64
—
64
—
64
ms
1
t
SREX
Self Refresh Exit Time
10
10
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-260
-360
-10
Units
Min.
2
Max.
—
Min.
2
Max.
—
Min.
3
Max.
—
t
DS
t
DH
t
DPL
Data In Set-up Time
ns
Data In Hold Time
1
—
1
—
1
—
ns
Data input to Precharge
Data In to Active Delay
CAS Latency = 2
Data In to Active Delay
CAS Latency = 3
DQM Write Mask Latency
15
—
15
—
15
—
ns
t
DAL2
5
—
5
—
5
—
CLK
t
DAL3
4
—
4
—
4
—
CLK
t
DQW
0
—
0
—
0
—
CLK
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