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| 型號： | AD5330BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT SNGL VOUT 20-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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AD5330/AD5331/AD5340/AD5341
Rev. A | Page 20 of 28
SUGGESTED DATABUS FORMATS
In most applications, GAIN and BUF are hard-wired. However,
if more flexibility is required, they can be included in a databus.
This enables the user to software program GAIN, giving the
option of doubling the resolution in the lower half of the DAC
range. In a bused system, GAIN and BUF can be treated as data
inputs because they are written to the device during a write
operation and take effect when LDAC is taken low. This means
that the reference buffers and the output amplifier gain of
multiple DAC devices can be controlled using common GAIN
and BUF lines.
In the case of the AD5330, this means that the databus must be
wider than eight bits. The AD5331 and AD5340 databuses must
be at least 10 bits and 12 bits wide, respectively, and are best
suited to a 16-bit databus system.
Examples of data formats for putting GAIN and BUF on a
16-bit databus are shown in Figure 40. Note that any unused bits
above the actual DAC data can be used for BUF and GAIN. DAC
devices can be controlled using common GAIN and BUF lines.
AD5331
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GAIN
X
BUF
AD5330
AD5340
X = UNUSED BIT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GAIN
X
BUF
DB9 DB8
X
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
GAIN
BUF
DB9 DB8
DB10
DB11
06852-
041
Figure 40. GAIN and BUF Data on a 16-Bit Bus
The AD5341 is a 12-bit device that uses byte load, so only four
bits of the high byte are actually used as data. Two of the unused
bits can be used for GAIN and BUF data by connecting them to
the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as
DATA
INPUTS
BUF
GAIN
LDAC
CLR
CS
WR
HBEN
AD5341
DB7
DB6
8-BIT
DATA BUS
0
68
52
-04
2
Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data
on 8-Bit Bus
In this case, the low byte is written to first in a write operation
with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into
GAIN and BUF registers but have no effect. The high byte is
then written to. Only the lower four bits of data are written into
the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and
BUF data.
LDAC is used to update the DAC, GAIN, and BUF values.
DB8
DB9
HIGH BYTE
LOW BYTE
X = UNUSED BIT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
XX
DB10
DB11
BUF
GAIN
06
85
2-
04
3
Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus
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| AD5330BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 115 ??A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5330BRUZ-REEL | 功能描述:IC DAC 8BIT SNGL VOUT 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 設(shè)計資源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 標(biāo)準(zhǔn)包裝:10,000 系列:- 設(shè)置時間:- 位數(shù):12 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 薄型，TSOT-23-8 供應(yīng)商設(shè)備封裝:TSOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:2.7M |
| AD5330BRUZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 115 ??A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5330BRUZ-REEL7 | 功能描述:IC DAC 8BIT SNGL VOUT 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 設(shè)計資源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 標(biāo)準(zhǔn)包裝:10,000 系列:- 設(shè)置時間:- 位數(shù):12 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 薄型，TSOT-23-8 供應(yīng)商設(shè)備封裝:TSOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:2.7M |
| AD5330BRUZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 115 ??A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
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