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| 型號(hào)： | IC41LV8512-50K |
| 英文描述： | 10:1 LVDS Serdes Transmitter 100-400 Mbps 28-SSOP -40 to 85 |
| 中文描述： | 為512k × 8位動(dòng)態(tài)隨機(jī)存儲(chǔ)器與江戶頁(yè)面模式 |
| 文件頁(yè)數(shù)： | 9/21頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | IC41LV8512-50K |
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IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
9
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
35
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Units
t
ACH
Column-Address Setup Time to
CAS
Precharge during WRITE Cycle
OE
Hold Time from
WE
during
READ-MODIFY-WRITE cycle
(18)
Data-In Setup Time
(15, 22)
Data-In Hold Time
(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS
to
WE
Delay Time during
READ-MODIFY-WRITE Cycle
(14)
CAS
to
WE
Delay Time
(14, 20)
Column-Address to
WE
Delay Time
(14)
EDO Page Mode READ or WRITE
Cycle Time
(24)
RAS
Pulse Width in EDO Page Mode
Access Time from
CAS
Precharge
(15)
EDO Page Mode READ-WRITE
Cycle Time
(24)
Data Output Hold after
CAS
LOW
Output Buffer Turn-Off Delay from
CAS
or
RAS
(13,15,19, 29)
Output Disable Delay from
WE
Last
CAS
going LOW to First
CAS
returning HIGH
(23)
CAS
Setup Time (CBR REFRESH)
(30, 20)
CAS
Hold Time (CBR REFRESH)
(30, 21)
OE
Setup Time prior to
RAS
during
HIDDEN REFRESH Cycle
Refresh Period (512 Cycles)
Transition Time (Rise or Fall)
(2, 3)
15
—
15
—
15
—
ns
t
OEH
8
—
10
—
15
—
ns
t
DS
t
DH
t
RWC
t
RWD
0
6
80
45
—
—
—
—
0
8
—
—
—
—
0
10
140
80
—
—
—
—
ns
ns
ns
ns
125
70
t
CWD
t
AWD
t
PC
25
30
12
—
—
—
34
42
20
—
—
—
36
49
25
—
—
—
ns
ns
ns
t
RASP
t
CPA
t
PRWC
35
—
40
100K
21
—
50
—
47
100K
27
—
50
—
56
100K
34
—
ns
ns
ns
t
COH
t
OFF
5
3
—
15
5
3
—
15
5
3
—
15
ns
ns
t
WHZ
t
CLCH
3
10
15
—
3
10
15
—
3
10
15
—
ns
ns
t
CSR
t
CHR
t
ORD
8
8
0
—
—
—
10
10
0
—
—
—
10
10
0
—
—
—
ns
ns
ns
t
REF
t
T
—
1
8
50
8
1
—
50
8
1
—
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)
One TTL Load and 50 pF (Vcc = 3.3V ±10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V ±10%);
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V ±10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5V ±10%, 3.3V ±10%)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC41C8512-50K | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50KI | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50T | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-50TI | 512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41C8512-60K | 512K x 8 bit Dynamic RAM with EDO Page Mode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC41LV8512-50KI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-50T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-50TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-60K | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
| IC41LV8512-60KI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 8 bit Dynamic RAM with EDO Page Mode |
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