- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360716 > IC42S16100-5TI 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號(hào)： | IC42S16100-5TI |
| 英文描述： | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k × 16位× 2組（16兆）同步動(dòng)態(tài)RAM |
| 文件頁數(shù)： | 31/78頁 |
| 文件大小： | 789K |
| 代理商： | IC42S16100-5TI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
IC42S16100
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
31
CAS
latency = 2, 3, burst length = 4
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
WDL
) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the
CAS
.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
PRE 0
WRITE A0
COMMAND
DQM
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
WDL
=0
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
MASKED BY DQM
PRE 0
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A2
D
IN
A3
t
DPL
WRITE (CA=A, BANK 0)
PRECHARGE (BANK 0)
CAS
Latency
t
WDL
3
0
2
0
t
DPL
1
1
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write data
recovery period (t
DPL
) has elapsed. Therefore, the
precharge command must be executed on one clock cycle
that follows the input of the last burst data item.
CAS
latency = 2, 3, burst length = 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S16100-5TIG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6T | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TI | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TIG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16100-5TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。