- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360716 > IC42S16100-5TI 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM PDF資料下載
參數(shù)資料
| 型號： | IC42S16100-5TI |
| 英文描述： | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k × 16位× 2組（16兆）同步動態(tài)RAM |
| 文件頁數(shù)： | 33/78頁 |
| 文件大?。?/td> | 789K |
| 代理商： | IC42S16100-5TI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
IC42S16100
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
33
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IC42S16100 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IC42S16100 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed within the ACT to PRE command period
(t
RAS
max.) following the burst stop command. After the
period (t
WBD
) required for burst data input to stop following
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (t
WBD
) is zero clock
cycles, regardless of the
CAS
latency.
CAS
latency = 2, burst length = 4
READ A0
COMMAND
UDQM
LDQM
I/O8-I/O15
I/O0-I/O 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the
CAS
latency, two clock cycles (t
QMD
) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to
the HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time t
QMD
later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte
output (pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS
latency = 2, 3, burst length = full page
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A
D
IN
A1
D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0)
BURST STOP
BST
PRE 0
INVALID DATA
PRECHARGE (BANK 0)
Don’t Care
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S16100-5TIG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6T | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TI | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TIG | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16100-5TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-6TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。