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參數(shù)資料
| 型號： | IC42S16100-7TG |
| 英文描述： | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k × 16位× 2組（16兆）同步動態(tài)RAM |
| 文件頁數(shù)： | 17/78頁 |
| 文件大?。?/td> | 789K |
| 代理商： | IC42S16100-7TG |
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IC42S16100
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
17
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
n-1
Current State
Operation
n
CS
RAS
CAS
WE
A11
A10 A9-A0
Self-Refresh
Undefined
Self-Refresh Recovery
(2)
Self-Refresh Recovery
(2)
Illegal
(2)
Illegal
(2)
Self-Refresh
Idle State After t
RC
Has Elapsed
Idle State After t
RC
Has Elapsed
Illegal
Illegal
Power-Down on the Next Cycle
Power-Down on the Next Cycle
Illegal
Illegal
Clock Suspend Termination on the Next Cycle
(2)
Clock Suspend
Undefined
Power-Down Mode Termination, Idle After
That Termination
(2)
Power-Down Mode
See the Operation Command Table
Bank Active Or Precharge
Auto-Refresh
Mode Register Set
See the Operation Command Table
See the Operation Command Table
See the Operation Command Table
Self-Refresh
(3)
See the Operation Command Table
Power-Down Mode
(3)
See the Operation Command Table
Clock Suspend on the Next Cycle
(4)
Clock Suspend Termination on the Next Cycle
Clock Suspend Termination on the Next Cycle
H
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
H
L
X
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
X
H
X
H
L
L
L
X
H
L
L
L
H
L
L
L
X
X
X
X
X
X
H
H
L
X
X
H
H
L
X
H
H
L
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Self-Refresh Recovery
Power-Down
L
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
L
H
H
H
H
H
L
L
L
L
L
X
H
L
H
L
X
H
L
L
L
L
H
L
L
L
L
X
X
X
X
X
X
X
H
L
L
L
X
H
L
L
L
X
X
X
X
X
X
X
X
H
L
L
X
X
H
L
L
X
X
X
X
X
X
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Both Banks Idle
OP CODE
X
X
X
X
OP CODE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other States
Notes:
1.
2.
H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH. The
minimum setup time (t
CKA
) required before all commands other than mode termination must be satisfied.
Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
The input must be command defined in the operation command table.
3.
4.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16100-7TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-7TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16101 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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