參數(shù)資料
型號: IC42S16100-7TG
英文描述: 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 為512k × 16位× 2組(16兆)同步動態(tài)RAM
文件頁數(shù): 25/78頁
文件大?。?/td> 789K
代理商: IC42S16100-7TG
IC42S16100
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
25
Read With Auto-Precharge
The read with auto-precharge command first executes a
burst read operation and then puts the selected bank in the
precharged state automatically. After the precharge com-
pletes, the bank goes to the idle state. Thus this command
performs a read command and a precharge command in
a single operation.
During this operation, the delay period (t
PQL
) between the
last burst data output and the start of the precharge
operation differs depending on the
CAS
latency setting.
When the
CAS
latency setting is two, the precharge
operation starts on one clock cycle before the last burst
data is output (t
PQL
= –1). When the
CAS
latency setting is
CAS
Latency
t
PQL
3
2
–2
–1
COMMAND
I/O
CLK
t
RP
t
PQL
READA 0
ACT 0
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
D
OUT
0
D
OUT
1
D
OUT
2
D
OUT
3
COMMAND
I/O
CLK
READA 0
ACT 0
t
RP
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
t
PQL
D
OUT
0
D
OUT
1
D
OUT
2
D
OUT
3
CAS
latency = 3, burst length = 4
CAS
latency = 2, burst length = 4
three, the precharge operation starts on two clock cycles
before the last burst data is output (t
PQL
= –2). Therefore,
the selected bank can be made active after a delay of t
RP
from the start position of this precharge operation.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length is
set to full page.
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