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參數(shù)資料
| 型號(hào)： | IC61LV256-8TI |
| 英文描述： | 32K x 8 Hight Speed SRAM with 3.3V |
| 中文描述： | 32K的× 8 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 122K |
| 代理商： | IC61LV256-8TI |
IC61LV256
Integrated Circuit Solution Inc.
AHSR027-0B
11/28/2003
5
AC TEST LOADS
Figure 1.
Figure 2.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Symbol
Parameter
Unit
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
HZOE
(2)
t
LZCE
(2)
t
HZCE
(2)
t
PU
(3)
t
PD
(4)
Read Cycle Time
8
—
10
—
12
—
15
—
ns
Address Access Time
—
8
—
10
—
12
—
15
ns
Output Hold Time
2
—
2
—
2
—
2
—
ns
CE
Access Time
—
8
—
10
—
12
—
15
ns
OE
Access Time
—
4
—
5
—
6
—
7
ns
OE
to Low-Z Output
0
—
0
—
0
—
0
—
ns
OE
to High-Z Output
—
4
—
5
—
5
—
6
ns
CE
to Low-Z Output
3
—
3
—
3
—
3
—
ns
CE
to High-Z Output
—
4
—
5
—
6
—
7
ns
CE
to Power-Up
0
—
0
—
0
—
0
—
ns
CE
to Power-Down
—
8
—
10
—
12
—
15
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100%
tested.
3. Not 100% tested.
319
30 pF
Including
jig and
scope
353
OUTPUT
3.3V
319
5 pF
jig and
scope
353
OUTPUT
3.3V
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