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參數(shù)資料
| 型號： | IC61LV256-8TI |
| 英文描述： | 32K x 8 Hight Speed SRAM with 3.3V |
| 中文描述： | 32K的× 8 Hight高速SRAM與3.3V |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 122K |
| 代理商： | IC61LV256-8TI |
IC61LV256
Integrated Circuit Solution Inc.
AHSR027-0B
11/28/2003
7
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Symbol
Parameter
Unit
t
WC
t
SCE
t
AW
Write Cycle Time
8
—
10
—
12
—
15
—
ns
CE
to Write End
7
—
8
—
8
—
10
—
ns
Address Setup Time
to Write End
7
—
8
—
8
—
10
—
ns
t
HA
Address Hold
from Write End
0
—
0
—
0
—
0
—
ns
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Address Setup Time
0
—
0
—
0
—
0
—
ns
WE
Pulse Width
7
—
10
—
12
—
15
—
ns
Data Setup to Write End
4.5
—
5
—
6
—
7
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
3.5
—
4
—
6
—
7
ns
WE
HIGH to Low-Z Output
0
—
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3.0V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
tested.
4. Tested with
OE
HIGH.
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