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參數(shù)資料
| 型號： | ICM7243AIPL |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 8-Character, Microprocessor- Compatible, LED Display Decoder Driver |
| 中文描述： | LED DISPLAY DRIVER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 109K |
| 代理商： | ICM7243AIPL |
9-32
Detailed Description
WR, CS, CS
- These pins are immediately functionally
ANDed, so all actions described as occurring on an edge of
WR, with CS and CS enabled, will occur on the equivalent
(last) enabling or (first) disabling edge of any of these
inputs. The delays from CS pins are slightly (about 5ns)
greater than from WR or CS due to the additional inverter
required on the former.
MODE
- The MODE pin input is latched on the falling edge
of WR (or its equivalent, see above). The location (in Data
Memory) where incoming data will be placed is determined
either from the Address pins or the Sequential Address
Counter. This is controlled by MODE input. MODE also
controls the function of A0/SEN, A1/CLR, and A2/DlSPlay
FULL lines.
Random Access Mode
- When the internal mode latch is
set for
Random Access (RA)
(MODE latched low), the
Address input on A0, A1 and A2 will be latched by the fall-
ing edge of WR (or its equivalent). Subsequent changes on
the Address lines will not affect device operation. This
allows use of a multiplexed 6-bit bus controlling both
address and data, with timing controlled by WR.
Sequential Access Mode
- If the internal latch is set for
Sequential Access (SA)
, (MODE latched high), the Serial
ENable input or SEN will be latched on the falling edge of
WR (or its equivalent). The CLR input is asynchronous, and
will force-clear the Sequential Address Counter to address
000 (CHARacter 1), and set all Data Memory contents to
100000 (blank) at any time. The DISPlay FULL output will
be active in
SA
mode to indicate the overflow status of the
Sequential Address Counter. If this output is low, and SEN
is (latched) high, the contents of the Counter will be used to
establish the Data Memory location for the Data input. The
Counter is then incremented on the rising edge of WR. If
SEN is low, or DISPlay FULL is high, no action will occur.
This allows easy “daisy-chaining” of display drivers for mul-
tiple character displays in a
Sequential Access
mode.
Changing Modes
- Care must be exercised in any
application involving changing from one mode to another.
The change will occur only on a falling edge of WR (or its
equivalent). When changing mode from
Access
to
Random Access
, note that A2/DlSPlay FULL
will be an output until WR has fallen low, and an Address
drive here could cause a conflict. When changing from
Random Access
to
Sequential Access
, A1/CLR should
be high to avoid inadvertent clearing of the Data Memory
and Sequential Address Counter. DISPlay FULL will
become active immediately after the rising edge of WR.
Sequential
Data Entry
- The input Data is latched on the rising edge of
WR (or its equivalent) and then stored in the Data Memory
location determined as described above. The six Data bits
can be multiplexed with the Address information on the
sAll Intersil semiconductor products are manufactured, assembled and tested under
Random Access
mode. Timing is controlled
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
By adding external capacitance to V
DD
at the OSC/OFF
http://www.intersil.com
pin, this frequency can be reduced as far as desired. Alter-
natively, an external signal can be injected on this pin. The
oscillator (or external) frequency is pre-divided by 64, and
then further divided by 8 in the Multiplex Counter, to drive
the CHARacter drive lines (see Figure 3). An inter-charac-
ter blanking signal is derived from the pre-divider. An addi-
tional comparator on the OSC/OFF input detects a level
lower than the relaxation oscillator's range, and blanks the
display, disables the DISPlay FULL output (if active), and
clears the pre-divider and Multiplex Counter. This puts the
circuit in a low-power-dissipation mode in which all outputs
are effectively open circuits, except for parasitic diodes to
the supply lines. Thus a display connected to the output
may be driven by another circuit (including another
ICM7243) without driver conflicts.
Display Output
- The output of the Multiplex Counter is
decoded and multiplexed into the address input of the Data
Memory, except during WR operations (in Sequential
Access mode, with SEN high and DISPlay FULL low),
when it scans through the display data. The address
decoder also drives the CHARacter outputs, except during
the inter-character blanking interval (nominally about 5
μ
s).
Each CHARacter output lasts nominally about 300
μ
s, and
is repeated nominally every 2.5ms, i.e., at a 400Hz rate
(times are based on internal oscillator without external
capacitor).
The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive the SEGment outputs. Both CHARacter and SEG-
ment outputs are disabled during WR operations (with SEN
high and DISPlay FULL Low for
Sequential Access
mode). The outputs may also be disabled by pulling
OSC/OFF low.
The decode pattern from 6 bits to 17 (15) segments is done
by a ROM pattern according to the ASCll font shown. Cus-
tom decode patterns can be arranged, within these limita-
tions, by consultation with the factory.
ICM7243
ISO9000
quality systems certification.
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| ICM7243AIPLZ | 功能描述:LED顯示驅(qū)動器 W/ANNEAL 40 -20 + 85 LED 8 CHAR DISP RoHS:否 制造商:Micrel 數(shù)位數(shù)量:5 片段數(shù)量: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-44 工作電源電壓:4.75 V to 11 V 最大電源電流:10 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| ICM7243B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:TIMERS COUNTERS AND DISPLAY DRIVERS |
| ICM7243BEV | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:TIMERS COUNTERS AND DISPLAY DRIVERS |
| ICM7243BIJL | 制造商:INTRSL 功能描述: |
| ICM7243BIPL | 功能描述:LED顯示驅(qū)動器 40 PDIP,-20 + 85, LED 8 CHAR DISPDRI 14S RoHS:否 制造商:Micrel 數(shù)位數(shù)量:5 片段數(shù)量: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PLCC-44 工作電源電壓:4.75 V to 11 V 最大電源電流:10 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
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