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參數(shù)資料
| 型號(hào)： | ICS1562BM-201-4LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大小： | 0K |
| 描述： | IC VIDEO CLK SYNTHESIZER 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，TTL，晶體 |
| 輸出： | CMOS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 1562BM-201-4LFT |
Figure 6
VCO GAIN
MAX FREQUENCY
4
120 MHz
5
200 MHz
6
260 MHz
7*
*SPECIAL APPLICATION. Contact factory for custom product above
260 MHz.
Phase Detector Gain: For most graphics applications and
divider ranges, set P[1, 0] = 10 and set P[2] = 1. Under
some circumstances, setting the P[2] bit “on” can reduce
jitter. During 1562 operation at exact multiples of the
crystal frequency, P[2] bit = 0 may provide the best jitter
performance.
Board Test Support
It is often desirable to statically control the levels of the output
pins for circuit board test. The ICS1562B supports this through
a register programmable mode, AUXEN. When this mode is
set, two register bits directly control the logic levels of the
CLK+/CLK- pins and the LOAD pin. This mode is activated
when the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
Power Supplies and Decoupling
The ICS1562B has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the video board as close
to the package as is possible.
The ICS1562B has a VDDO pin which is the supply of +5 volt
power to all output drivers. This pin should be connected to the
power plane (or bus) using standard high-frequency decou-
pling practice. That is, capacitors should have low series induc-
tance and be mounted close to the ICS1562B.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We recom-
mend that RC decoupling or zener regulation be provided for
this pin (as shown in the recommended application circuitry).
This will allow the PLL to “track” through power supply
fluctuations without visible effects. See Figure 6 for typical
external circuitry.
ICS1562B
6
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| ICS1562BM-201LF | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS1562BM-201LFT | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS1562BM-201T | 功能描述:IC VIDEO CLK SYNTHESIZER 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS1562BM-XXX | 制造商:ICS 制造商全稱:ICS 功能描述:User Programmable Differential Output Graphics Clock Generator |
| ICS1567 | 制造商:ICS 制造商全稱:ICS 功能描述:Differential Output Video Dot Clock Generator |
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