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參數(shù)資料
| 型號(hào)： | ICS1660 |
| 英文描述： | GT 13C 13#16 PIN RECP WALL RM |
| 中文描述： | 來(lái)電線路識(shí)別（ICLID）接收機(jī)環(huán)檢測(cè) |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | ICS1660 |
Pin Descriptions
PIN NUMBER
DIP
SO
NAME
DESCRIPTION
1
1
VDD
Supply voltage pin to external circuits. Output of 5.0 volt regulator.
2
2
RING
Ring detect output signal to the host microprocessor.
3
3
POSTF
Post loop filter signal used by demodulator.
4
4
LFILTER
Loop filter for PLL.
5
5
LINEAFILTER
Filter input from line “A.”
6
6
VCOSET
Center frequency adjustment pin.
7
7
LINEA
“Tip” input from telephone line.
8
8
LINEB
“Ring” input from telephone line.
9
9
VSS
Ground.
10
11
FILTER2
Active filter pin.
11
12
FILTEROUT
Active filter pin.
12
13
AMPIN
Input from active filter.
13
14
FILTER3
Active filter pin.
14
15
LINEBFILTER
Filter input from line “B.”
15
16
FILTER1
Active filter pin.
16
17
PWR
Logic input signal to switch from low current standby mode.
17
18
FSK/BAT
Multiplexed output signal controlled by PWR pin. In standby mode, this is a
low battery (active low) signal. During FSK demodulation, this is the data line
to the
μ
P (mark = high).
18
19
VIN
Input power supply pin.
10 20
NC on SOIC
ICS1660
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1660M | GT 13C 13#16 SKT RECP WALL RM |
| ICS1660N | GT 17C 17#16 SKT RECP WALL RM |
| ICS1694AM-012 | CPU System Clock Generator |
| ICS1694AM-013 | CPU System Clock Generator |
| ICS1694AM-014 | CPU System Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1660M | 制造商:ICS 制造商全稱:ICS 功能描述:Incoming Call Line Identification (ICLID) Receiver with Ring Detection |
| ICS1660N | 制造商:ICS 制造商全稱:ICS 功能描述:Incoming Call Line Identification (ICLID) Receiver with Ring Detection |
| ICS16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICS16857C | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICS16859 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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