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參數(shù)資料
| 型號： | ICS1660 |
| 英文描述： | GT 13C 13#16 PIN RECP WALL RM |
| 中文描述： | 來電線路識別（ICLID）接收機(jī)環(huán)檢測 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 108K |
| 代理商： | ICS1660 |
Input/Output Specifications
Digital
RING and FSKBAT outputs are standard CMOS outputs with
voltage swings between V
SS
and V
DD
.
PWR is a logic input. A level converter circuit is on chip to
allow the logic signal that swing between V
SS
and V
DD
to be
internally converted to signals that swing between V
SS
and
V
IN
. It should be noted that to minimize power consumption
caused by through current in logic gates, the PWR input should
always swing to within 100 mV of V
SS
or V
DD
. The PWR
input signal is low when the
ICS1660
is in lower power mode
waiting for an incoming call.
The LFILTER output is a standard CMOS output powered from
VDD. This output has an internal resistor with a typical value
of 30k
. This is used in conjunction with the external capacitor
shown in the block diagram to form the loop filter for the PLL.
Analog
The value of the ring detect is as previously discussed 35.0V
RMS typical. The actual value is set by the choice of the
external resistors that are connected to the LINEA and LINEB
inputs. The matching of these resistors to the internal 8.1k
resistors is also a factor. The signal level at the chip that will
cause a ring is the bandgap voltage, (1.25V) or below.
The chip is designed for an input signal level of -12.5dbm to
-28.5dbm into 900 ohms. This translates to a signal that is
between 100 mV and 636 mV peak to peak.
The filter section should be connected as shown in the block
diagram. Using the external capacitors as shown, and assuming
nominal values on the internal resistors, the corner frequencies
are 900 HZ and 3860 HZ.
An external resistor with a value of approximately 330k
is
connected between the LFILTER and POSTF pads. This resis-
tor along with the external capacitor shown in the block dia-
gram form the post filter. This post filter is used in conjunction
with the comparator to do the FSK demodulation.
Absolute Maximum Ratings
*
(Voltages referenced to V
SS
)
Supply Voltage . . . . . . . . V
IN
. . . . . . . . . -0.5V to +10V
Voltage at any Input . . . . . . . . . . . . . . . . . -0.5V to V
DD
+ 0.5V
Operation Temperature Range
. . . . . . . . . . . -55
°
C to +125
°
C
Storage Temperature Range . . . . . . . . . . . . . -50
°
C to 150
°
C
*
Absolute maximum ratings are those values beyond which the safety of this device cannot be guaranteed.
These values are NOT RECOMMENDED operating conditions.
ICS1660
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS1660M | GT 13C 13#16 SKT RECP WALL RM |
| ICS1660N | GT 17C 17#16 SKT RECP WALL RM |
| ICS1694AM-012 | CPU System Clock Generator |
| ICS1694AM-013 | CPU System Clock Generator |
| ICS1694AM-014 | CPU System Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1660M | 制造商:ICS 制造商全稱:ICS 功能描述:Incoming Call Line Identification (ICLID) Receiver with Ring Detection |
| ICS1660N | 制造商:ICS 制造商全稱:ICS 功能描述:Incoming Call Line Identification (ICLID) Receiver with Ring Detection |
| ICS16857 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICS16857C | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer |
| ICS16859 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR 13-Bit to 26-Bit Registered Buffer |
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