參數(shù)資料
型號: ICS1893BFLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 114/133頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標(biāo)準(zhǔn)包裝: 30
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
其它名稱: 1893BFLF
Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
81
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
Note: An MDIO read of these bits provides a history of the greatest progress achieved by the
auto-negotiation process. In addition, the MDIO read latches the present state of the
Auto-Negotiation State Machine for a subsequent read.
7.12.4 100Base-TX Receive Signal Lost (bit 17.10)
The 100Base-TX Receive Signal Lost bit indicates to an STA whether the ICS1893BF has lost its
100Base-TX Receive Signal. If this bit is set to a logic:
Zero, it indicates the Receive Signal has remained valid since either the last read or reset of this register.
One, it indicates the Receive Signal was lost since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note: This bit has no definition in 10Base-T mode.
7.12.5 100Base PLL Lock Error (bit 17.9)
The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893BF has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
Zero, it indicates that a PLL Lock Error has not occurred since either the last read or reset of this register.
One, it indicates that a PLL Lock Error has occurred since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note: This bit has no definition in 10Base-T mode.
Table 7-19. Auto-Negotiation State Machine (Progress Monitor)
Auto-Negotiation State Machine
Auto-Negotiation Progress Monitor
Auto-
Negotiation
Complete Bit
(Bit 17.4)
Auto-
Negotiation
Monitor Bit 2
(Bit 17.13)
Auto-
Negotiation
Monitor Bit 1
(Bit 17.12)
Auto-
Negotiation
Monitor Bit 0
(Bit 17.11)
Idle
0000
Parallel Detected
0001
Parallel Detection Failure
0010
Ability Matched
0011
Acknowledge Match Failure
0100
Acknowledge Matched
0101
Consistency Match Failure
0110
Consistency Matched
0111
Auto-Negotiation Completed
Successfully
1000
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