參數(shù)資料
型號: ICS1893BFLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 115/133頁
文件大?。?/td> 0K
描述: PHYCEIVER LOW PWR 3.3V 48-SSOP
標準包裝: 1
系列: PHYceiver™
類型: PHY 收發(fā)器
規(guī)程: MII
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應商設備封裝: 48-SSOP
包裝: 標準包裝
產(chǎn)品目錄頁面: 1252 (CN2011-ZH PDF)
其它名稱: 800-1017-6
ICS1893BF, Rev. F, 5/13/10
May, 2010
82
Chapter 7 Management Register Set
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.12.6 False Carrier (bit 17.8)
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1893BF in 100Base
mode.
A False Carrier occurs when the ICS1893BF begins evaluating potential data on the incoming 100Base
data stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
Zero, it indicates a False Carrier has not been detected since either the last read or reset of this register.
One, it indicates a False Carrier was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note: This bit has no definition in 10Base-T mode.
7.12.7 Invalid Symbol (bit 17.7)
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1893BF.
When the ICS1893BF is receiving a packet, it examines each received Symbol to ensure the data is error
free. If an error occurs, the port indicates this condition to the MAC by asserting the RXER signal. In
addition, the ICS1893BF sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic:
Zero, it indicates an Invalid Symbol has not been detected since either the last read or reset of this
register.
One, it indicates an Invalid Symbol was detected since either the last read or reset of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note: This bit has no definition in 10Base-T mode.
7.12.8 Halt Symbol (bit 17.6)
The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the
ICS1893BF.
During reception of a valid packet, the ICS1893BF examines each symbol to ensure that the data being
passed to the MAC Interface is error free. In addition, it looks for special symbols such as the Halt Symbol.
If a Halt Symbol is encountered, the ICS1893BF indicates this condition to the MAC.
If this bit is set to a logic:
Zero, it indicates a Halt Symbol has not been detected since either the last read or reset of this register.
One, it indicates a Halt Symbol was detected in the packet since either the last read or reset of this
register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see Section
Note: This bit has no definition in 10Base-T mode.
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