- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9984 > ICS1893BFLFT (IDT, Integrated Device Technology Inc)PHYCEIVER LOW PWR 3.3V 48-SSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | ICS1893BFLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 89/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1252 (CN2011-ZH PDF) |
| 其它名稱： | 800-1017-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁當(dāng)前第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
Chapter 7 Management Register Set
ICS1893BF, Rev. F, 5/13/10
May, 2010
59
ICS1893BF Data Sheet Rev. F - Release
Copyright 2009, IDT, Inc.
All rights reserved.
7.3.6 IEEE Reserved Bits (bits 1.10:7)
The IEEE reserves these bits for future use. When an STA:
Reads a reserved bit, the ICS1893BF returns a logic zero.
Writes a reserved bit, the STA must use the default value specified in this data sheet.
Both the ISO/IEC standard and the ICS1893BF reserve the use of some Management Register bits. ICS
uses some reserved bits to invoke ICS1893BF test functions. To ensure proper operation of the
ICS1893BF, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA
write the default value to all reserved bits during all Management Register write operations.
Reserved bits 1.10:7 are Command Override Write (CW) bits. When bit 16.15, the Command Register
Override bit, is logic:
Zero, the ICS1893BF prevents all STA writes to CW bits.
One, an STA can modify the value of these bits.
7.3.7 MF Preamble Suppression (bit 1.6)
Status Register bit 1.6 is the Management Frame (MF) Preamble Suppression bit. The ICS1893BF sets bit
1.6 to inform the STA of its ability to receive frames that do not have a preamble. When this bit is logic:
Zero, the ICS1893BF is indicating it cannot accept frames with a suppressed preamble.
One, the ICS1893BF is indicating it can accept frames that do not have a preamble.
Although the ICS1893BF supports Management Frame Preamble Suppression, its default value for bit 1.6
is logic zero. This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does
not have this capability. As the means of enabling this feature, the ICS1893BF implements bit 1.6 as a
Command Override Write bit, instead of as a Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to
enable MF Preamble Suppression in the ICS1893BF. [See the description of bit 16.15, the Command
Override Write Enable bit, in Section 7.11, “Register 16: Extended Control Register”.]
7.3.8 Auto-Negotiation Complete (bit 1.5)
An STA reads bit 1.5 to determine the state of the ICS1893BF auto-negotiation process. The ICS1893BF
sets the value of this bit using two criteria. When its Auto-Negotiation sublayer is:
Disabled, the ICS1893BF sets bit 1.5 to logic zero.
Enabled, the ICS1893BF sets bit 1.5 to a value based on the state of the Auto-Negotiation State
Machine. In this case, it sets bit 1.5 to logic one only upon completion of the auto-negotiation process.
This setting indicates to the STA that a link is arbitrated and the contents of Management Registers 4, 5,
and 6 are valid. For details on the auto-negotiation process, see Section 6.2, “Functional Block:
Bit 1.5 is a latching high (LH) bit. (For more information on latching high and latching low bits, see Section
Note: An Auto-Negotiation Restart does not clear an LH bit. However, performing two consecutive reads
of this register provides the present state of the bit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT723631L20PF | IC FIFO SYNC 512X36 120-TQFP |
| VE-26F-IW-F2 | CONVERTER MOD DC/DC 72V 100W |
| MS27473T18F35SC | CONN PLUG 66POS STRAIGHT W/SCKT |
| MS27467P17B35SA | CONN PLUG 55POS STRAIGHT W/SCKT |
| MS27508E20B2P | CONN RCPT 65POS BOX MNT W/PINS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1893BFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BK | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BKI | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BKILF | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):1/1 規(guī)程:RS422，RS485 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 其它名稱:ISL31470EIBZ-T7ACT |
| ICS1893BKILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 56-VQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1 系列:- 類型:線路收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):5/3 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:Digi-Reel® 產(chǎn)品目錄頁面:918 (CN2011-ZH PDF) 其它名稱:296-25096-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。