![](http://datasheet.mmic.net.cn/230000/ICS2008B_datasheet_15578838/ICS2008B_3.png)
3
ICS2008B
ICS2008B Rev D 4/05/05
Pin Descriptions
TYPE:
A – Analog P – Power I – Input O – Output
2008 2008B ICS2008
PIN NUMBER
TQFP
PIN
NAME
TYPE
DESCRIPTION
PLCC
12, 10
18, 16
Y1, Y2
AI
Video inputs from camera or other source. NOTE: This is also the Y
(Luma) input for S-VHS and HI-8 systems.
C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this
pin should be tied to its respective Y input.
Data Threshold bypass input.
SYNC Threshold bypass input.
Clamp Threshold bypass input.
Video output. This is also the Y (Luma) output in S-Video mode.
C (Chroma) output for S-VHS and HI-8 systems.
Color Frame A/B input. This input is self biased (See Applications).
LTC SYNC input. This input is self biased (See Applications).
SMPTE LTC input+. This input is self biased (See Applications).
SMPTE LTC input–. This input is self biased (See Applications).
SMPTE LTC output
SMPTE LTC receive clock output.
SMPTE VITC output to video mixer circuit.
VITC gate indicates VITC code is being output for video overlay.
UART Transmit data
UART Receive data
Clear to Send
Ready to Send
14.318 MHz crystal input.
14.318 MHz crystal oscillator output.
Tie to +5 VDC
Address bus
Read Enable (active low)
Write Enable (active low)
SMPTE port chip select (active low)
UART chip select (active low)
Master reset (active high)
Bi-directional data bus
Interrupt Request (active high)
Analog V
DD
Analog Ground
Digital V
DD
Digital
11, 9
17, 15
C1, C2
AI
15
13
14
8
7
41
42
44
43
1
20
22
21
18
16
17
19
4
3
2
21
19
20
14
13
3
4
6
5
7
26
28
27
24
22
23
25
10
9
8
DTHRESH
STHRESH
CTHRESH
Y OUT
C OUT
FRAME
CLICK
LTCIN+
LTCIN–
LTCOUT
LRCLK
VITCOUT
VITCGATE
TxD
RxD
CTS*
RTS*
XTAL1
XTAL2
LFC
A1-A0
IOR*
IOW*
SMPTECS*
UARTCS*
RESET
D7-D0
INTR
AVDD
AVSS
VDD
VSS
AI
AI
AI
AO
AO
AI
AI
AI
AI
AO
O
O
O
O
I
I
O
I
O
AI
I
I
I
I
I
I
I/O
O
P
P
P
P
24, 23
27
30
25
26
40
38–31
39
5
6
29
28
30, 29
33
36
31
32
2
44–37
1
11
12
35
34