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參數(shù)資料
| 型號： | ICS308RT |
| 英文描述： | SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER |
| 中文描述： | 串行可編程四鎖相環(huán)VERSACLOCK合成器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 134K |
| 代理商： | ICS308RT |
S
ERIAL
P
ROGRAMMABLE
Q
UAD
PLL V
ERSA
C
LOCK
S
YNTHESIZER
MDS 308 F
2
Revision 090704
Integrated Circuit Systems
●
525 Race Street, San Jose, CA 95126
●
tel (408) 297-1201
●
www.icst.com
ICS308
Pin Assignment
Pin Descriptions
16
1
15
2
14
DATA
STROBE
3
13
X2
4
12
X1/ICLK
SCLK
5
11
CLK9
6
PDTS
7
VDD
8
GND
VDD
VDD
GND
CLK1
CLK5
CLK2
CLK6
9
10
CLK3
CLK7
CLK4
CLK8
20
19
18
17
20 pin (150 mil) SSOP (QSOP)
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
DATA
Input
Serial data input.
2
X2
XO
Crystal Output. Connect this pin to a crystal. Float for clock input.
3
X1/ICLK
XI
Connect this pin to a crystal or external clock input.
4
CLK9
Output
Output clock 9. Default of Reference frequency output when unprogrammed.
5
VDD
Power
Connect to +3.3 V.
6
GND
Power
Connect to Ground.
7
CLK1
Output
Output clock 1. Default of Reference frequency output when unprogrammed.
8
CLK2
Output
Output clock 2. Default of Reference frequency output when unprogrammed.
9
CLK3
Output
Output clock 3. Default of Reference frequency output when unprogrammed.
10
CLK4
Output
Output clock 4. Default of Reference frequency output when unprogrammed.
11
CLK8
Output
Output clock 8. Default of Reference frequency output when unprogrammed.
12
CLK7
Output
Output clock 7. Default of Reference frequency output when unprogrammed.
13
CLK6
Output
Output clock 6. Default of Reference frequency output when unprogrammed.
14
CLK5
Output
Output clock 5. Default of Reference frequency output when unprogrammed.
15
GND
Power
Connect to Ground.
16
VDD
Power
Connect to +3.3 V.
17
VDD
Power
Connect to +3.3 V.
18
PDTS
Input
Powers down entire chip, tri-states all outputs when low. Internal pull-up.
19
SCLK
Input
Serial Shift register clock. See timing diagram.
20
STROBE
Input
Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.
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