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參數(shù)資料
| 型號(hào)： | ICS3726M-02LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VCXO HI PERF 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 壓控晶體振蕩器（VCXO） |
| PLL： | 無 |
| 輸入： | 晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 36MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 3726M-02LFT |
ICS3726-02
HIGH PERFORMANCE VCXO
VCXO
IDT / ICS HIGH PERFORMANCE VCXO
3
ICS3726-02
REV C 030706
External Component Selection
The ICS3726-02 requires a minimum number of
external components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01
F should be connected
between VDD and GND on pins 6 and 4 as close to the
ICS3726-02 as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used
trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Quartz Crystal
The ICS3726-02 VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters (shown below) must
be used, and the layout guidelines discussed in the
following section shown must be followed.
The oscillation frequency of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS3726-02 incorporates on-chip
variable load capacitors that pull (change) the
frequency of the crystal. The crystal specified for use
with the ICS3726-02 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 10
pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pF
Shunt Capacitance, C0
7 pF max
C0/C1 Ratio
250 max
Equivalent Series Resistance
35
max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS3726-02. There should be no via’s
between the crystal pins and the X1 and X2 device pins.
There should be no signal traces underneath or close to
the crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on
the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF. This chip has internal load
capacitors and is designed to work with surface mount
crystals with 10 pF load capacitance.
The procedure for determining the value of these
capacitors can be found in application note MAN05.
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| ICS3726M-02T | 制造商:ICS 制造商全稱:ICS 功能描述:HIGH PERFORMANCE VCXO |
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| ICS3726M-12LFT | 制造商:ICS 制造商全稱:ICS 功能描述:HIGH PERFORMANCE VCXO |
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