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參數(shù)資料
| 型號： | ICS5342 |
| 元件分類： | 顯示控制器 |
| 英文描述： | PALETTE-DAC DSPL CTLR, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | ICS5342 |
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ICS5342
GENDAC
4
Internal Registers
RS2
RS1
RS0
Register Name
Description (all registers can be written to and read from)
The GENDAC has a single pixel address register which can be
accessed through either register address 0,0,0 or 0,1,1 – reading
from either register gives the same result.
Writing a value to address 0,0,0:
– species an address within the color palette RAM
– initializes the Color Value register
Writing a value to address 0,1,1:
– species an address within the color palette RAM
– loads Color Value register with contents of location in
addressed RAM palette and then:
– increments Pixel Address register
0
1
Pixel Address
WRITE
Writing to this 8-bit register is done before writing one or more
color values to color palette RAM.
0
1
Pixel Address
READ
Writing to this 8-bit register is done before reading one or more
color values from color palette RAM.
0
1
Color Value
The 18-bit Color Value register acts as a buffer between the
microprocessor interface and the color palette. A value may be
read from or written to this register using a three-byte transfer
sequence. The color value is contained in the least signicant 6
bits, D0-D5, of the byte read – the most signicant 2 bits are set
to zero. The same 6 bits are used when writing a byte. When
reading or writing, data is transferred in the same order – red
byte rst, then green, then blue. Each transfer between the Color
Value register and the color palette replaces the normal pixel
mapping operations of the GENDAC for a single pixel.
After writing three denitions to this register, its contents are
written to the location in the color palette RAM specied by the
Pixel Address register, before that register increments.
After reading three denitions from this register, the contents of
the location in the color palette RAM specied by the Pixel
Address registers are copied into the Color Value register, and
the Pixel Address register increments.
0
1
0
Pixel Mask
The 8-bit Pixel Mask register can be used to mask selected bits
of the Pixel Address value applied to the Pixel Address inputs
(P7-P0). A one in a position in the mask register leaves the corre-
sponding bit in the Pixel Address unaltered, while a zero sets
that bit to zero. The Pixel Mask register does not affect the Pixel
Address generated by the microprocessor interface when the pal-
ette RAM is being accessed.
1
0
PLL Address
WRITE
Writing to this 8-bit register is performed prior to writing one or
more PLL programming values to the PLL Parameter register.
1
PLL Address
READ
Writing to this 8-bit register is performed prior to reading one or
more PLL programming values from the PLL Parameter register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS5342-1 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-2 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-3 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342ADD | 制造商:ICS 制造商全稱:ICS 功能描述:Addendum to ICS5342 Data Sheet |
| ICS5342V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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