參數(shù)資料
型號: ICS5342
元件分類: 顯示控制器
英文描述: PALETTE-DAC DSPL CTLR, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 32/36頁
文件大?。?/td> 1017K
代理商: ICS5342
ICS5342
GENDAC
5
1
0
Command
This 8-bit register selects color mode, for instance 8-bit Pseudo
Color, Hi-Color, True Color, or XGA, and DAC power down.
The registers are reset to pseudo color mode on power up.
1
0
1
PLL Parameter
There are 16 PLL parameter registers accessible as indexed by
Read/Write registers. Parameter registers 0F and 0D-00 are two
bytes long and 0E is one byte long. Register 0E is a control reg-
ister. The bits of this register include clock select and enable
functions, the rest contain PLL frequency parameters. After writ-
ing the start index address in the PLL address register, these reg-
isters can be accessed in successive two (or one) bytes. The
address register auto increments after one (0E) or two bytes to
access the entire register
Internal Registers
RS2
RS1
RS0
Register Name
Description (all registers can be written to and read from)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS5342-1 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC
ICS5342-2 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC
ICS5342-3 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC
ICS5342ADD 制造商:ICS 制造商全稱:ICS 功能描述:Addendum to ICS5342 Data Sheet
ICS5342V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC