- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67685 > ICS810001BK-21 (INTEGRATED DEVICE TECHNOLOGY INC) 810001 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 PDF資料下載
參數(shù)資料
| 型號： | ICS810001BK-21 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 810001 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封裝： | 5 X 5 MM, 0.95 MM HEIGHT, MO-220VHHD-2, VFQFN-32 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 485K |
| 代理商： | ICS810001BK-21 |
810001BK-21
www.icst.com/products/hiperclocks.html
REV. A AUGUST 12, 2005
15
Integrated
Circuit
Systems, Inc.
ICS810001-21
FEMTOCLOCKSDUAL VCXO VIDEO PLL
PRELIMINARY
NOTES ON SETTING THE VALUE OF C
P
As another general rule, the following relationship should be
maintained between components C
S and CP in the loop filter:
C
P establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of C
P based on
a C
S value that would be used for a damping factor of 1. This will
minimize baseband peaking and loop instability that can lead to
output jitter.
C
P also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A C
P value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and C
P is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
The best way to set the value of C
P is to use the filter response
software available from ICS (please refer to the following section).
C
P should be increased in value until it just starts affecting the
passband peak.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 27/30 to ground and between pins 38/31 to ground.
These are optional crystal load capacitors which can be used to
center tune the external pullable crystal (the crystal frequency
can only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response can be found at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
C
P =
C
S
20
EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to
ensure output stability. A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
1
2
3
64
27/30
28/31
LF1
LF0
ISET
C
S
R
S
C
P
R
SET
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
shouldnot run underneath the device, the loop filter or crystal
components.
ICS810001-21
FEMTOCLOCKS DUAL VCXO VIDEO PLL
TSD
IDT / ICS FEMTOCLOCKS DUAL VCXO VIDEO PLL
ICS810001-21
15
相關PDF資料 |
PDF描述 |
|---|---|
| ICS81006AKILF | 40 MHz, OTHER CLOCK GENERATOR, QCC20 |
| ICS81006AKIT | 40 MHz, OTHER CLOCK GENERATOR, QCC20 |
| ICS81006AKILF | 40 MHz, OTHER CLOCK GENERATOR, QCC20 |
| ICS81006AKLFT | 40 MHz, OTHER CLOCK GENERATOR, QCC20 |
| ICS81006AKLFT | 40 MHz, OTHER CLOCK GENERATOR, QCC20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS810001BK-21T | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL |
| ICS810001BK-22LF | 功能描述:IC CLK SYNC DL VCXO PLL 32 VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS810001BK-22LFT | 功能描述:IC CLK SYNC DL VCXO PLL 32 VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS810001DK-21LF | 功能描述:IC CLK GEN SYNC VCXO DL 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
| ICS810001DK-21LFT | 功能描述:IC CLK GEN SYNC VCXO DL 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
發(fā)布緊急采購，3分鐘左右您將得到回復。