VCXO JITTER ATTENUATOR & FEM" />
參數(shù)資料
型號(hào): ICS813323BGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 20/22頁
文件大?。?/td> 0K
描述: IC ATTENUATOR/MULTIPLIER 24TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 扇出配送,頻率變換器,抖動(dòng)衰減器,壓控晶體振蕩器(VCXO)
PLL: 帶旁路
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
其它名稱: 813323BGLFT
ICS813323BG REVISION A APRIL 13, 2010
7
2010 Integrated Device Technology, Inc.
ICS813323 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCKMULTIPLIER
Table 5B. AC Characteristics, VCC = 3.3V ± 5%, VCCO = 2.5V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop badwidth. Refer to VCXO-PLL Loop
Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: Jitter performance using crystal inputs.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 5: Lock Time measured from power-up to stable output frequency.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fIN
Input Frequency
PSEL = ÷1
19.44
MHz
PSEL = ÷4
77.76
MHz
PSEL = ÷8
155.52
MHz
PSEL = ÷32
622.08
MHz
fOUT
Output Frequency
FSEL = ÷1
622.08
MHz
FSEL = ÷4
155.52
MHz
FSEL = ÷8
77.76
MHz
FSEL = ÷32
19.44
MHz
tjit()
RMS Phase Jitter, (Random),
NOTE 1
155.52MHz fOUT, 19.44MHz crystal,
Integration Range: 12kHz – 20MHz
1.4
2
ps
tjit(per)
Period Jitter, RMS; NOTE 2
3.3
5.5
ps
tsk(o)
Output Skew; NOTE 3, 4
50
ps
tR / tF
Output Rise/Fall Time
20% to 80%
240
780
ps
odc
Output Duty Cycle
45
55
%
tLOCK
VCXO & FemtoClock PLL Lock
Time; NOTE 5
Reference Clock Input is ±50ppm from
Nominal Frequency
70
ms
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