參數(shù)資料
型號(hào): ICS83021AMILFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 5/10頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFFER DVR TRANSLA 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™
類型: 緩沖器/驅(qū)動(dòng)器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/無(wú)
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVCMOS,LVTTL
頻率 - 最大: 350MHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
其它名稱: 83021AMILFT
ICS83021I
1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
IDT / ICS LVCMOS/LVTTL TRANSLATOR
4
ICS83031AMI REV. C OCTOBER 31, 2008
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay, NOTE 1
≤ 350MHz
1.7
2.0
2.3
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
500
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range
(637kHz – 10MHz)
0.21
ps
tR / tF
Output Rise/Fall Time
0.8V to 2V
100
250
400
ps
odc
Output Duty Cycle
≤ 166MHz
45
50
55
%
166MHz <
≤ 350MHz
40
50
60
%
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay, NOTE 1
≤ 350MHz
1.9
2.2
2.5
ns
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
500
ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range
(637kHz – 10MHz)
0.21
ps
tR / tF
Output Rise/Fall Time
20% to 80%
250
550
ps
odc
Output Duty Cycle
≤ 250MHz
45
50
55
%
250MHz <
≤ 350MHz
40
50
60
%
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