參數(shù)資料
型號(hào): ICS840004BGI-01LFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 4/18頁(yè)
文件大小: 0K
描述: IC FREQ SYNTHESIZER 20TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類(lèi)型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
ICS840004I-01
FEMTOCLOCKS CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
IDT / ICS LVCMOS/LVTTL FREQUENCY SYNTHESIZER
12
ICS840004BGI-01 REV. C FEBRUARY 9, 2009
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied
from XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can
be left floating. Though not required, but for additional protection,
a 1k
resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-downs; additional resistance is
not required but can be added for additional protection. A 1k
resistor can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend
that there is no trace attached.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS840004I-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01F bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10 resistor along with
a 10
F bypass capacitor be connected to the V
DDA pin.
Figure 1. Power Supply Filtering
VDD
VDDA
3.3V
10
10F
.01F
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