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參數(shù)資料
| 型號： | ICS840004BGILFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 159.375MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
ICS840004BGI REVISION B JULY 6, 2009
5
2009 Integrated Device Technology, Inc.
ICS840004I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fout
Output Frequency
F_SEL[1:0] = 00
186.67
212.5
226.66
MHz
F_SEL[1:0] = 01
140
159.375
170
MHz
F_SEL[1:0] = 10
93.33
106.25
113.33
MHz
F_SEL[1:0] = 11
46.67
53.125
56.66
MHz
tsk(o)
Output Skew: NOTE 1, 2
60
MHz
tjit()
RMS Phase Jitter (Random);
NOTE 3
212.5MHz, Integration Range:
637kHz – 10MHz
0.49
ps
159.375MHz, Integration Range:
637kHz – 10MHz
0.55
ps
156.25MHz, Integration Range:
1.875MHz – 20MHz
0.56
ps
106.25MHz, Integration Range:
637kHz – 10MHz
0.79
ps
53.125MHz, Integration Range:
637kHz – 10MHz
0.65
ps
tR / tF
Output Rise/Fall Time
20% to 80%
250
800
ps
odc
Output Duty Cycle
F_SEL[1:0] = 00
40
60
%
F_SEL[1:0] = 01
42
58
%
F_SEL[1:0] = 10 or 11
48
52
%
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