IDT / ICS HCSL CLOCK GENERATOR 10 " />
參數(shù)資料
型號(hào): ICS841608AKILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/17頁
文件大小: 0K
描述: IC CLOCK GENERATOR 32-VFQFPN
產(chǎn)品培訓(xùn)模塊: PCI-Express
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 時(shí)鐘發(fā)生器,扇出配送,多路復(fù)用器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: HCSL
電路數(shù): 1
比率 - 輸入:輸出: 2:8
差分 - 輸入:輸出: 無/是
頻率 - 最大: 125MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-VFQFPN 裸露焊盤(4x4)
包裝: 帶卷 (TR)
其它名稱: 841608AKILFT
IDT / ICS HCSL CLOCK GENERATOR
10
ICS841608AKI REV. A JUNE 18, 2008
ICS841608I
FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR
FIGURE 5. ICS841608I SCHEMATIC EXAMPLE
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS841608I application
schematic. In this example, the device is operated at V
DD
= 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 =
27pF and C2 = 27pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 may be slightly
adjusted for optimizing frequency accuracy. Two examples of
HCSL terminations are shown in this schematic. The decoupling
capacitors should be located as close as possible to the power
pin.
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
Ω resistor can be tied
from XTAL_IN to ground.
REF_IN INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS
All control pins have internal pulldowns; additional resistance is
not required but can be added for additional protection. A 1k
Ω
resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
HCSL OUTPUTs
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
C3
0. 1u
+
-
R8
50
VDD
X1
25MHz
TL4
Zo = 50
VDD
Set Logic
Input to
'0'
RD2
1K
TL3
Zo = 50
To Logic
Input
pins
C1
27pF
U1
ICS841608I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
XTAL_I N
XTAL_OUT
MR/nOE
VDD
Q0
nQ0
Q1
nQ1
GN
D
Q2
nQ
2
Q3
nQ
3
VD
D
Q4
nQ
4
Q5
nQ5
GND
Q6
nQ6
Q7
nQ7
VDD
GN
D
VD
D
RE
F
_
IN
RE
F
_
S
E
L
VD
D
A
BY
PAS
S
IR
E
F
FS
E
L
+
-
R6
50
MR/nOE
FS
E
L
Recommended for PCI
Express Point-to-Point
Connection
VDD=3.3V
VDD
Set Logic
Input to
'1'
RE
F
_
S
E
L
R4
33
VDD
RD1
Not I nstall
R1
10
R7
50
VDD
VDDA
C2
27pF
(U1:6)
RU1
1K
Logic Control Input Examples
(U1:14)
VDD
TL2
Zo = 50
To Logic
Input
pins
VDD
C7
.1uf
VDD
TL1
Zo = 50
18pF
VD
D
R3
33
(U1:31)
R5
50
BYP
ASS
Recommended for
PCI Express Add-In
Card
VDD
RU2
Not I nst all
C6
.1uf
C8
.1uf
C4
10u
C5
0.1u
HCSL Termination
(U1:24)
R2
475
VDD
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