參數(shù)資料
型號： ICS8422002AGILFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 12/16頁
文件大小： 0K
描述： IC SYNTHESIZER LVHSTL 20-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
系列： HiPerClockS™, FemtoClock™
類型： 頻率合成器
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： LVHSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 226.66MHz
除法器/乘法器： 是/是
電源電壓： 2.375 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
其它名稱： 8422002AGILFT
ICS8422002AGI REVISION A AUGUST 12, 2009
5
2009 Integrated Device Technology, Inc.
ICS8422002I Data Sheet
FEMTOCLOCK CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, VDDO = 1.8V ±0.2V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
F_SEL[1:0] = 00
186.67
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
tsk(o)
Output Skew; NOTE 1, 2
35
ps
tjit()
RMS Phase Jitter (Random);
NOTE 3
212.5MHz, (637kHz – 10MHz)
0.59
ps
187.5MHz, (637kHz – 10MHz)
0.53
ps
159.375MHz, (637kHz – 10MHz)
0.56
ps
106.25MHz, (1.875MHz – 20MHz)
0.56
ps
53.125MHz, (637kHz – 10MHz)
0.66
ps
tR / tF
Output Rise/Fall Time
20% to 80%
275
875
ps
odc
Output Duty Cycle
N
≠ 348
52
%
N = 3
40
60
%
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
F_SEL[1:0] = 00
186.67
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
tsk(o)
Output Skew; NOTE 1, 2
35
ps
tjit()
RMS Phase Jitter (Random);
NOTE 3
212.5MHz, (637kHz – 10MHz)
0.60
ps
187.5MHz, (637kHz – 10MHz)
0.72
ps
159.375MHz, (637kHz – 10MHz)
0.64
ps
106.25MHz, (1.875MHz – 20MHz)
0.55
ps
53.125MHz, (637kHz – 10MHz)
0.68
ps
tR / tF
Output Rise/Fall Time
20% to 80%
250
650
ps
odc
Output Duty Cycle
N
≠ 348
52
%
N = 3
40
60
%
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