- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67689 > ICS843002CY-31T (SPECTRUM CONTROL INC) 700 MHz, OTHER CLOCK GENERATOR, PQFP64 PDF資料下載
參數(shù)資料
| 型號： | ICS843002CY-31T |
| 廠商： | SPECTRUM CONTROL INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, EXPOSED PAD, MS-026BCD, TQFP-64 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大小： | 270K |
| 代理商： | ICS843002CY-31T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
22
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PRELIMINARY
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 7B. LVPECL OUTPUT TERMINATION
FIGURE 7A. LVPECL OUTPUT TERMINATION
designed to drive 50
Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 7A and
7B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
EXPOSED PAD
Expose Metal Pad
(GROUND PAD)
GROUND PLANE
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
THERM AL VIA
SOLDER M ASK
FIGURE 6. P.C. BOARD FOR EXPOSED PADTHERMAL RELEASE PATH EXAMPLE
THERMAL RELEASE PATH
The exposed metal pad provides heat transfer from the
device to the P.C. board. The exposed metal pad is ground
pad connected to ground plane through thermal via. The
exposed pad on the device to the exposed metal pad on the
PCB is contacted through solder as shown in Figure 6. For
further information, please refer to the Application Note on
Surface Mount Assembly of Amkor’s Thermally /Electrically
Enhance Leadframe Base Package, Amkor Technology.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS843003AGLF | 700 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-01LFT | 156.25 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LFT | 637.5 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LF | 680 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AGI-01 | 170 MHz, OTHER CLOCK GENERATOR, PDSO24 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843002I | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-40 | 制造商:ICS 制造商全稱:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-41 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-72 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。