參數(shù)資料
型號: ICS843004AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/20頁
文件大小: 0K
描述: IC SYNTHESIZER LVPECL 24-TSSOP
標準包裝: 62
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL: 帶旁路
輸入: 晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 無/是
頻率 - 最大: 226.66MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -30°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: 800-1953-5
843004AGLF
ICS843004AGLF-ND
ICS843004
FEMTOCLOCKS LVCMOS/CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS843004AG REV. C JANUARY 19, 2008
Table 3C. LVPECL DC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
NOTE 1: Outputs termination with 50
to V
CCO – 2V.
Table 4. Crystal Characteristics
NOTE: Characterized using an 18pF parallel resonant crystal.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = VCCA = VCCO = 3.3V ± 5%, VEE =0V, TA = -30°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plots.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Current; NOTE 1
VCCO – 1.4
VCCO – 0.9
A
VOL
Output Low Current; NOTE 1
VCCO – 2.0
VCCO – 1.7
A
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
Frequency
23.33
26.5625
28.33
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7pF
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency Range
F_SEL[1:0] = 00
186.67
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
tsk(o)
Output Skew; NOTE 1, 2
30
ps
tjit()
RMS Phase Jitter, (Random);
NOTE 3
212.5MHz,
(637kHz – 10MHz)
0.70
ps
159.375MHz,
(637kHz – 10MHz)
0.75
ps
156.25MHz,
(637kHz – 10MHz)
0.58
ps
106.25MHz, (637kHz – 10MHz)
0.81
ps
53.125MHz, (637kHz – 10MHz)
0.98
ps
tR / tF
Output Rise/Fall Time
20% to 80%
300
600
ps
odc
Output Duty Cycle
F_SEL[1:0]
≠ 00
49
51
%
F_SEL[1:0] = 00
45
55
%
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