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參數(shù)資料
| 型號： | ICS843034AYLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 750 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 726K |
| 代理商： | ICS843034AYLF |
IDT / ICS 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
18
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION SCHEMATIC EXAMPLE
Figure 9shows a schematic example of using an ICS843034. In
this example, the CLK/nCLK input is driven by a 3.3V LVPECL
driver. The data sheet also shows the CLK/nCLK input driven by
various types of drivers. The crystal inputs are parallel resonant
crystal with load capacitor CL=18pF. The frequency fine tuning
capacitors C1 and C2 are 22pF. This schematic example shows
hardwired logic control input handling. The logic inputs can also
be driven by 3.3V LVCMOS drivers. It is recommended to have
one decouple capacitor per power pin. In general, the decoupling
capacitor values are ranged from 0.01uF to 0.1uF.
Each
decoupling capacitor should be located as close as possible to
the power pin. The low pass filter R9, C11 and C16 for clean
3.3V
Zo = 50 Ohm
Zo = 50
Set Logic
Input to
'0'
C2
22p
To Logic
Input
pins
VCCO_REF
Alternative
Termination
Exmaple
VCCO_REF=3.3V
VCC
LVCMOS
VCCA
C8
0.1u
C9
0.1u
R8
43
R11
50
R12
50
C11
0.01u
R3
50
VCC
X1
CL=18pF
R1
50
C3
22p
Set Logic
Input to
'1'
R7
82.5
RD2
1K
R4
133
RU2
SPARE
C4
22p
VCC
R9
10
C6
0.1u
R2
50
R10
50
C1
22p
C7
0.1u
+
-
Zo = 50 Ohm
VCCO=3.3V
Zo = 50 Ohm
Logic Input Pin Examples
Zo = 50 Ohm
+
-
VCC
VCCO
VCC
RD1
SPARE
RU1
1K
LVPECL
VCC=3.3V
C5
0.1u
R5
82.5
U1
ICS843034
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
M8
NB0
NB1
NB2
OE_REF
OE_A
OE_B
VCC
NA0
NA1
NA2
VEE
TE
S
T
VC
C
FO
UTA
0
nF
O
U
T
A
0
V
CCO
_
A
FO
UTB
0
nF
O
U
T
B
0
V
CCO
_
B
RE
F_
CL
K
V
CCO
_
RE
F
P_
D
IV
VEE
X_OUT1
X_IN1
X_OUT0
X_IN0
TEST_CLK
SEL1
SEL0
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
M7
M6
M5
M4
M3
M2
M1
M0
VC
O_S
EL
nP_
L
O
A
D
nC
L
K
CL
K
Zo = 50
C16
10u
R6
133
To Logic
Input
pins
VCCO
X1
CL=18pF
FIGURE 9. ICS843034 APPLICATION SCHEMATIC EXAMPLE
analog supply should also be located as close to the VCCA pin
as possible. Only two examples of 3.3V LVPECL termination are
shown in this schematic example. Additional LVPECL terminations
can be found in the LVPECL Termination Application Note. The
data sheet also shows 2.5V LVPECL terminations. The REF_CLK
is LVCMOS driver with 7
output impedance. Series termination
for REF_CLK is shown in the example. Additional LVCMOS
termination can be found in the LVCMOS Application Note. If the
REF_CLK is not used, it is recommended to disable this output
by setting REF_OE to logic low. To disable REF_CLK, REF_OE
pin can be left floating (default logic low by internal 51K pull down)
or pull down using an external 1k
resistor.
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| ICS8430AYI-71LFT | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| ICS8430BY-71LF | 700 MHz, OTHER CLOCK GENERATOR, PQFP32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843034AYLFT | 功能描述:IC CLK SYNTHESIZER LVPECL 48LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS843034AYT | 制造商:ICS 制造商全稱:ICS 功能描述:MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843051 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS8430-51 | 制造商:ICS 制造商全稱:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843051AG | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
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